AArch64ASIMDAssembler

java.lang.Object
- org.graalvm.compiler.asm.aarch64.AArch64ASIMDAssembler

Direct Known Subclasses:

AArch64ASIMDMacroAssembler
```
public abstract class AArch64ASIMDAssembler
extends Object
```
This class encapsulates the AArch64 Advanced SIMD (ASIMD) assembler support. The documentation below heavily references the Arm Architecture Reference Manual version G-a. The latest copy of the manual can be found here.
In order to minimize confusion between ASIMD and similarly named General-Purpose/FP instructions, each ASIMD instruction has capitalized a suffix which describes, in the order described in Section C7.2, the type of each of the instruction's operands using in the following form:
- G: General purpose register.
- V: ASIMD register.
- X: ASIMD register index (V[idx]).
- S: ASIMD scalar register. This is primarily used to * perform integer operations within vector registers without having to transfer the values back * to the general-purpose register, or performing an operation across a single register, such as addv.
- I: Immediate Operand.

Nested Class Summary

Nested Classes
Modifier and Type	Class and Description
`static class`	`AArch64ASIMDAssembler.ASIMDImmediateTable` Calculates and maintains a mapping of all possible ASIMD immediate values.
`static class`	`AArch64ASIMDAssembler.ASIMDInstruction`
`static class`	`AArch64ASIMDAssembler.ASIMDSize` Enumeration of all different SIMD operation sizes.
`static class`	`AArch64ASIMDAssembler.ElementSize` Enumeration of all different lane types of SIMD register.
`static class`	`AArch64ASIMDAssembler.ImmediateOp` Enumeration for all vector instructions which can have an immediate operand.

Constructor Summary

Constructors
Modifier Constructor and Description

protected AArch64ASIMDAssembler(AArch64Assembler asm)

Constructors
Modifier	Constructor and Description
`protected`	`AArch64ASIMDAssembler(AArch64Assembler asm)`

Method Summary

All Methods Instance Methods Concrete Methods
Modifier and Type	Method and Description
`void`	`absVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src)` C7.2.1 Integer absolute value. `for i in 0..n-1 do dst[i] = int_abs(src[i])`
`void`	`addpVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.5 Add pairwise vector.
`void`	`addSSS(AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.2 Integer add scalar. `dst[0] = int_add(src1[0], src2[0])`
`void`	`addvSV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize elementSize, Register dst, Register src)` C7.2.6 Add across vector. `dst = src[0] + ....+ src[n].`
`void`	`addVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.2 Integer add vector. `for i in 0..n-1 do dst[i] = int_add(src1[i], src2[i])`
`void`	`aesd(Register dst, Register src)` C7.2.7 AES single round decryption.
`void`	`aese(Register dst, Register src)` C7.2.8 AES single round encryption.
`void`	`aesimc(Register dst, Register src)` C7.2.9 AES inverse mix columns.
`void`	`aesmc(Register dst, Register src)` C7.2.10 AES mix columns.
`void`	`andVVV(AArch64ASIMDAssembler.ASIMDSize size, Register dst, Register src1, Register src2)` C7.2.11 Bitwise and vector. `for i in 0..n-1 do dst[i] = src1[i] & src2[i]`
`void`	`bicVI(AArch64ASIMDAssembler.ASIMDSize size, Register dst, long imm)` C7.2.20 Bitwise bit clear. This instruction performs a bitwise and between the SIMD register and the complement of the provided immediate value.
`void`	`bicVVV(AArch64ASIMDAssembler.ASIMDSize size, Register dst, Register src1, Register src2)` C7.2.21 Bitwise bit clear (vector, register). This instruction performs a bitwise and between the first source and the complement of the second source.
`void`	`bifVVV(AArch64ASIMDAssembler.ASIMDSize size, Register dst, Register src1, Register src2)` C7.2.22 Bitwise insert if false. This instruction inserts each bit from the first source register into the destination register if the corresponding bit of the second source register is 0, otherwise leave the bit in the destination register unchanged.
`void`	`bitVVV(AArch64ASIMDAssembler.ASIMDSize size, Register dst, Register src1, Register src2)` C7.2.23 Bitwise insert if true. This instruction inserts each bit from the first source register into the destination register if the corresponding bit of the second source register is 1, otherwise leave the bit in the destination register unchanged.
`void`	`bslVVV(AArch64ASIMDAssembler.ASIMDSize size, Register dst, Register src1, Register src2)` C7.2.24 Bitwise select. This instruction sets each bit in the destination register to the corresponding bit from the first source register when the original destination bit was 1, otherwise from the second source register.
`void`	`cmeqVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.27 Compare bitwise equal.
`void`	`cmeqZeroVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src)` C7.2.28 Compare bitwise equal to zero.
`void`	`cmgeVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.29 Compare signed greater than or equal.
`void`	`cmgeZeroVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src)` C7.2.30 Compare signed greater than or equal to zero.
`void`	`cmgtVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.31 Compare signed greater than.
`void`	`cmgtZeroVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src)` C7.2.32 Compare signed greater than zero.
`void`	`cmhiVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.33 Compare unsigned higher.
`void`	`cmhsVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.34 Compare unsigned higher or same.
`void`	`cmleZeroVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src)` C7.2.35 Compare signed less than or equal to zero.
`void`	`cmltZeroVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src)` C7.2.36 Compare signed less than zero.
`void`	`cmtstVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.37 Compare bitwise test bits nonzero.
`void`	`cntVV(AArch64ASIMDAssembler.ASIMDSize size, Register dst, Register src)` C7.2.38 Population Count per byte. `dst[0...n] = countBitCountOfEachByte(src[0...n]), n = size/8.`
`void`	`dupSX(AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src, int index)` C7.2.39 Duplicate vector element to scalar. Note that, regardless of the source vector element's index, the value is always copied into the beginning of the destination register (offset 0).
`void`	`dupVG(AArch64ASIMDAssembler.ASIMDSize dstSize, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src)` C7.2.40 Duplicate general-purpose register to vector. `dst(simd) = src(gp){n}`
`void`	`dupVX(AArch64ASIMDAssembler.ASIMDSize dstSize, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src, int index)` C7.2.39 Duplicate vector element to vector. `dst[0..n-1] = src[index]{n}`
`protected void`	`emitInt(int x)`
`void`	`eorVVV(AArch64ASIMDAssembler.ASIMDSize size, Register dst, Register src1, Register src2)` C7.2.41 Bitwise exclusive or vector. `for i in 0..n-1 do dst[i] = src1[i] ^ src2[i]`
`void`	`extVVV(AArch64ASIMDAssembler.ASIMDSize size, Register dst, Register src1, Register src2, int src1LowIdx)` C7.2.43 Extract from pair of vectors.
`void`	`fabsVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src)` C7.2.45 Floating-point absolute value. `for i in 0..n-1 do dst[i] = fp_abs(src[i])`
`void`	`facgeVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.47 Floating-point absolute compare greater than or equal.
`void`	`facgtSSS(AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.48 Floating-point absolute compare greater than.
`void`	`facgtVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.48 Floating-point absolute compare greater than.
`void`	`faddVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.49 floating point add vector. `for i in 0..n-1 do dst[i] = fp_add(src1[i], src2[i])`
`void`	`fcmeqVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.56 Floating-point compare equal.
`void`	`fcmeqZeroVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src)` C7.2.57 Floating-point compare equal to zero.
`void`	`fcmgeVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.58 Floating-point compare greater than or equal.
`void`	`fcmgeZeroVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src)` C7.2.59 Floating-point compare greater than or equal to zero.
`void`	`fcmgtVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.60 Floating-point compare greater than.
`void`	`fcmgtZeroVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src)` C7.2.61 Floating-point compare greater than zero.
`void`	`fcmleZeroVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src)` C7.2.64 Floating-point compare less than or equal to zero.
`void`	`fcmltZeroVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src)` C7.2.65 Floating-point compare less than zero.
`void`	`fcvtlVV(AArch64ASIMDAssembler.ElementSize srcESize, Register dst, Register src)` C7.2.74 Floating-point convert to higher precision long.
`void`	`fcvtnVV(AArch64ASIMDAssembler.ElementSize srcESize, Register dst, Register src)` C7.2.79 Floating-point convert to lower precision narrow.
`void`	`fcvtzsVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src)` C7.2.90 Floating-point convert to to signed integer, rounding toward zero.
`void`	`fdivVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.97 floating point divide vector. `for i in 0..n-1 do dst[i] = fp_div(src1[i], src2[i])`
`void`	`fmaxVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.101 floating-point maximum. `for i in 0..n-1 do dst[i] = fp_max(src1[i], src2[i])`
`void`	`fminVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.111 floating-point minimum. `for i in 0..n-1 do dst[i] = fp_min(src1[i], src2[i])`
`void`	`fmlaVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.122 Floating-point fused multiply-add to accumulator. `for i in 0..n-1 do dst[i] += fp_multiply(src1[i], src2[i])`
`void`	`fmlsVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.126 Floating-point fused multiply-subtract from accumulator. `for i in 0..n-1 do dst[i] -= fp_multiply(src1[i], src2[i])`
`void`	`fmovVI(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, long imm64)` C7.2.132 Floating-point move immediate. `dst = imm64{1,2}`
`void`	`fmulVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.135 floating point multiply vector. `for i in 0..n-1 do dst[i] = fp_mul(src1[i], src2[i])`
`void`	`fnegVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src)` C7.2.139 Floating-point negate. `for i in 0..n-1 do dst[i] = -src[i]`
`void`	`fsqrtVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src)` C7.2.171 Floating-point square root. `for i in 0..n-1 do dst[i] = fp_sqrt(src[i])`
`void`	`fsubVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.173 floating point subtract vector. `for i in 0..n-1 do dst[i] = fp_sub(src1[i], src2[i])`
`void`	`insXG(AArch64ASIMDAssembler.ElementSize eSize, Register dst, int index, Register src)` C7.2.176 Insert vector element from general-purpose register. `dst[index] = src` Note the rest of the dst register is unaltered.
`void`	`ld1MultipleV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, AArch64Address addr)` C7.2.177 Load multiple single-element structures to one register. This instruction loads multiple single-element structures from memory and writes the result to one register.
`void`	`ld1MultipleVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst1, Register dst2, AArch64Address addr)` C7.2.177 Load multiple single-element structures to two registers. This instruction loads multiple single-element structures from memory and writes the result to two registers.
`void`	`ld1MultipleVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst1, Register dst2, Register dst3, AArch64Address addr)` C7.2.177 Load multiple single-element structures to three registers. This instruction loads multiple single-element structures from memory and writes the result to three registers.
`void`	`ld1MultipleVVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst1, Register dst2, Register dst3, Register dst4, AArch64Address addr)` C7.2.177 Load multiple single-element structures to four registers. This instruction loads multiple single-element structures from memory and writes the result to four registers.
`void`	`ld1rV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, AArch64Address addr)` C7.2.179 Load one single-element structure and replicate to all lanes (of one register). This instruction loads a single-element structure from memory and replicates the structure to all lanes of the register.
`void`	`mlaVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.196 Multiply-add to accumulator. `for i in 0..n-1 do dst[i] += int_multiply(src1[i], src2[i])`
`void`	`mlsVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.198 Multiply-subtract from accumulator. `for i in 0..n-1 do dst[i] -= int_multiply(src1[i], src2[i])`
`void`	`moviVI(AArch64ASIMDAssembler.ASIMDSize size, Register dst, long imm)` C7.2.204 Move immediate. `dst = imm{1,2}`
`void`	`mulVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.206 Integer multiply vector. `for i in 0..n-1 do dst[i] = int_mul(src1[i], src2[i])`
`void`	`mvniVI(AArch64ASIMDAssembler.ASIMDSize size, Register dst, long imm)` C7.2.208 Move inverted immediate. `dst = ~(imm{1,2})`
`void`	`negVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src)` C7.2.209 Negate. `for i in 0..n-1 do dst[i] = -src[i]`
`void`	`notVV(AArch64ASIMDAssembler.ASIMDSize size, Register dst, Register src)` C7.2.210 Bitwise not vector. `for i in 0..n-1 do dst[i] = ~src[i]`
`void`	`ornVVV(AArch64ASIMDAssembler.ASIMDSize size, Register dst, Register src1, Register src2)` C7.2.211 Bitwise inclusive or not vector. `for i in 0..n-1 do dst[i] = src1[i] \| ~src2[i]`
`void`	`orrVI(AArch64ASIMDAssembler.ASIMDSize size, Register dst, long imm)` C7.2.212 Bitwise inclusive or. `dst = dst \| imm{1,2}`
`void`	`orrVVV(AArch64ASIMDAssembler.ASIMDSize size, Register dst, Register src1, Register src2)` C7.2.213 Bitwise inclusive or vector. `for i in 0..n-1 do dst[i] = src1[i] \| src2[i]`
`void`	`rev16VV(AArch64ASIMDAssembler.ASIMDSize size, Register dst, Register src)` C7.2.219 Reverse elements in 16-bit halfwords. This instruction reverses the order of 8-bit elements in each halfword.
`void`	`rev32VV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize revGranularity, Register dst, Register src)` C7.2.220 Reverse elements in 32-bit words. This instruction reverses the order of elements of size revGranularity in each 32-bit word.
`void`	`rev64VV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize revGranularity, Register dst, Register src)` C7.2.221 Reverse elements in 64-bit words. This instruction reverses the order of elements of size revGranularity in each 64-bit word.
`void`	`saddlvSV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize elementSize, Register dst, Register src)` C7.2.231 Signed add across long vector. `dst = src[0] + ....+ src[n].`
`void`	`scvtfVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src)` C7.2.234 Signed integer convert to floating-point.
`void`	`shlVVI(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src, int shiftAmt)` C7.2.254 shift left (immediate). `for i in 0..n-1 do dst[i] = src[i] << imm`
`void`	`smaxVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.268 Signed maximum. `for i in 0..n-1 do dst[i] = int_max(src1[i], src2[i])`
`void`	`sminVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.271 Signed minimum. `for i in 0..n-1 do dst[i] = int_min(src1[i], src2[i])`
`void`	`smlalVVV(AArch64ASIMDAssembler.ElementSize srcESize, Register dst, Register src1, Register src2)` C7.2.275 Signed Multiply-Add Long. `for i in 0..n-1 do dst[i] += int_multiply(src1[i], src2[i])`
`void`	`smlslVVV(AArch64ASIMDAssembler.ElementSize srcESize, Register dst, Register src1, Register src2)` C7.2.277 Signed Multiply-Subtract Long. `for i in 0..n-1 do dst[i] -= int_multiply(src1[i], src2[i])`
`void`	`smovGX(AArch64ASIMDAssembler.ElementSize dstESize, AArch64ASIMDAssembler.ElementSize srcESize, Register dst, Register src, int index)` C7.2.279 Signed move vector element to general-purpose register. `dst (gp) = sign-extend(src[index]) (simd).`
`void`	`sshllVVI(AArch64ASIMDAssembler.ElementSize srcESize, Register dst, Register src, int shiftAmt)` C7.2.316 Signed shift left long (immediate).
`void`	`sshlVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.315 signed shift left (register). `for i in 0..n-1 do if(byte(src2[i] > 0 dst[i] = (src1[i] << byte(src2[i] else dst[i] = (src1[i] >> byte(src2[i])`
`void`	`sshrVVI(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src, int shiftAmt)` C7.2.317 signed shift right (immediate). `for i in 0..n-1 do dst[i] = src[i] >> imm`
`void`	`st1MultipleV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register src, AArch64Address addr)` C7.2.321 Store multiple single-element structures from one register. This instruction stores elements to memory from one register.
`void`	`st1MultipleVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register src1, Register src2, AArch64Address addr)` C7.2.321 Store multiple single-element structures from two registers. This instruction stores elements to memory from two registers.
`void`	`st1MultipleVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register src1, Register src2, Register src3, AArch64Address addr)` C7.2.321 Store multiple single-element structures from three registers. This instruction stores elements to memory from three registers.
`void`	`st1MultipleVVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register src1, Register src2, Register src3, Register src4, AArch64Address addr)` C7.2.321 Store multiple single-element structures from four registers. This instruction stores elements to memory from four registers.
`void`	`subSSS(AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.334 Integer subtract scalar. `dst[0] = int_sub(src1[0], src2[0])`
`void`	`subVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.334 Integer subtract vector. `for i in 0..n-1 do dst[i] = int_sub(src1[i], src2[i])`
`void`	`tblVVV(AArch64ASIMDAssembler.ASIMDSize size, Register dst, Register table, Register index)` C7.2.339 Table vector lookup (single register table variant). This instruction is used to perform permutations at a byte granularity.
`void`	`tblVVVV(AArch64ASIMDAssembler.ASIMDSize size, Register dst, Register table1, Register table2, Register index)` C7.2.339 Table vector lookup (two register table variant). This instruction is used to perform permutations at a byte granularity.
`void`	`tbxVVV(AArch64ASIMDAssembler.ASIMDSize size, Register dst, Register table, Register index)` C7.2.440 Table vector lookup extension (single register table variant). This instruction is used to perform permutations at a byte granularity.
`void`	`trn1VVV(AArch64ASIMDAssembler.ASIMDSize dstSize, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.341 Transpose vectors (primary).
`void`	`trn2VVV(AArch64ASIMDAssembler.ASIMDSize dstSize, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.342 Transpose vectors (secondary).
`void`	`uaddlvSV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize elementSize, Register dst, Register src)` C7.2.350 Unsigned add across long vector. `dst = src[0] + ....+ src[n].`
`void`	`umaxvSV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize elementSize, Register dst, Register src)` C7.2.362 Unsigned maximum across vector. `dst = uint_max(src[0], ..., src[n]).`
`void`	`uminvSV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize elementSize, Register dst, Register src)` C7.2.365 Unsigned minimum across vector. `dst = uint_min(src[0], ..., src[n]).`
`void`	`umlalVVV(AArch64ASIMDAssembler.ElementSize srcESize, Register dst, Register src1, Register src2)` C7.2.367 Unsigned Multiply-Add Long. `for i in 0..n-1 do dst[i] += uint_multiply(src1[i], src2[i])`
`void`	`umlslVVV(AArch64ASIMDAssembler.ElementSize srcESize, Register dst, Register src1, Register src2)` C7.2.369 Unsigned Multiply-Subtract Long. `for i in 0..n-1 do dst[i] -= uint_multiply(src1[i], src2[i])`
`void`	`umovGX(AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src, int index)` C7.2.371 Unsigned move vector element to general-purpose register. `dst (gp) = src[index] (simd).`
`void`	`ushll2VVI(AArch64ASIMDAssembler.ElementSize srcESize, Register dst, Register src, int shiftAmt)` C7.2.391 Unsigned shift left long (immediate).
`void`	`ushllVVI(AArch64ASIMDAssembler.ElementSize srcESize, Register dst, Register src, int shiftAmt)` C7.2.391 Unsigned shift left long (immediate).
`void`	`ushlVVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.390 unsigned shift left (register). `for i in 0..n-1 do if(byte(src2[i] > 0) dst[i] = (src1[i] << byte(src2[i]) else dst[i] = (src1[i] >>> byte(src2[i])`
`void`	`ushrSSI(AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src, int shiftAmt)` C7.2.392 unsigned shift right (immediate) scalar. `for i in 0..n-1 do dst[i] = src[i] >>> imm`
`void`	`ushrVVI(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src, int shiftAmt)` C7.2.392 unsigned shift right (immediate) vector. `dst = src >>> imm`
`void`	`uzp1VVV(AArch64ASIMDAssembler.ASIMDSize dstSize, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.399 Unzip vectors (primary).
`void`	`uzp2VVV(AArch64ASIMDAssembler.ASIMDSize dstSize, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.400 Unzip vectors (secondary).
`void`	`xtn2VV(AArch64ASIMDAssembler.ElementSize dstESize, Register dst, Register src)` C7.2.402 Extract narrow.
`void`	`xtnVV(AArch64ASIMDAssembler.ElementSize dstESize, Register dst, Register src)` C7.2.402 Extract narrow.
`void`	`zip1VVV(AArch64ASIMDAssembler.ASIMDSize dstSize, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.403 Zip vectors (primary).
`void`	`zip2VVV(AArch64ASIMDAssembler.ASIMDSize dstSize, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src1, Register src2)` C7.2.404 Zip vectors (secondary).

Methods inherited from class java.lang.Object
clone, equals, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait

- Constructor Detail
  - AArch64ASIMDAssembler
```
protected AArch64ASIMDAssembler(AArch64Assembler asm)
```
- Method Detail
  - emitInt
```
protected void emitInt(int x)
```
  - absVV
```
public void absVV(AArch64ASIMDAssembler.ASIMDSize size,
                  AArch64ASIMDAssembler.ElementSize eSize,
                  Register dst,
                  Register src)
```
    C7.2.1 Integer absolute value.
    for i in 0..n-1 do dst[i] = int_abs(src[i])
    
    Parameters:
    
    size - register size.
    
    eSize - element size.
    
    dst - SIMD register.
    
    src - SIMD register.
  - addSSS
```
public void addSSS(AArch64ASIMDAssembler.ElementSize eSize,
                   Register dst,
                   Register src1,
                   Register src2)
```
    C7.2.2 Integer add scalar.
    dst[0] = int_add(src1[0], src2[0])
    Note that only 64-bit (DoubleWord) operations are available.
    
    Parameters:
    
    eSize - element size. Must be of type ElementSize.DoubleWord
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - addVVV
```
public void addVVV(AArch64ASIMDAssembler.ASIMDSize size,
                   AArch64ASIMDAssembler.ElementSize eSize,
                   Register dst,
                   Register src1,
                   Register src2)
```
    C7.2.2 Integer add vector.
    for i in 0..n-1 do dst[i] = int_add(src1[i], src2[i])
    
    Parameters:
    
    size - register size.
    
    eSize - element size.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - addpVVV
```
public void addpVVV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.5 Add pairwise vector.
    
    From the manual: "This instruction creates a vector by concatenating the vector elements of the first source SIMD&FP register after the vector elements of the second source SIMD&FP register, reads each pair of adjacent vector elements from the concatenated vector, adds each pair of values together, places the result into a vector, and writes the vector to the destination SIMD&FP register."
    
    Parameters:
    
    size - register size.
    
    eSize - element size.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - addvSV
```
public void addvSV(AArch64ASIMDAssembler.ASIMDSize size,
                   AArch64ASIMDAssembler.ElementSize elementSize,
                   Register dst,
                   Register src)
```
    C7.2.6 Add across vector.
    dst = src[0] + ....+ src[n].
    
    Parameters:
    
    size - register size.
    
    elementSize - width of each addition operand.
    
    dst - SIMD register.
    
    src - SIMD register.
  - aesd
```
public void aesd(Register dst,
                 Register src)
```
    C7.2.7 AES single round decryption.
    
    Parameters:
    
    dst - SIMD register.
    
    src - SIMD register.
  - aese
```
public void aese(Register dst,
                 Register src)
```
    C7.2.8 AES single round encryption.
    
    Parameters:
    
    dst - SIMD register.
    
    src - SIMD register.
  - aesimc
```
public void aesimc(Register dst,
                   Register src)
```
    C7.2.9 AES inverse mix columns.
    
    Parameters:
    
    dst - SIMD register.
    
    src - SIMD register.
  - aesmc
```
public void aesmc(Register dst,
                  Register src)
```
    C7.2.10 AES mix columns.
    
    Parameters:
    
    dst - SIMD register.
    
    src - SIMD register.
  - andVVV
```
public void andVVV(AArch64ASIMDAssembler.ASIMDSize size,
                   Register dst,
                   Register src1,
                   Register src2)
```
    C7.2.11 Bitwise and vector.
    for i in 0..n-1 do dst[i] = src1[i] & src2[i]
    
    Parameters:
    
    size - register size.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - bicVI
```
public void bicVI(AArch64ASIMDAssembler.ASIMDSize size,
                  Register dst,
                  long imm)
```
    C7.2.20 Bitwise bit clear.
    This instruction performs a bitwise and between the SIMD register and the complement of the provided immediate value. dst = dst & ~(imm{1,2})
    
    Parameters:
    
    size - register size.
    
    dst - SIMD register.
    
    imm - long value to move. If size is 128, then this value is copied twice
  - bicVVV
```
public void bicVVV(AArch64ASIMDAssembler.ASIMDSize size,
                   Register dst,
                   Register src1,
                   Register src2)
```
    C7.2.21 Bitwise bit clear (vector, register).
    This instruction performs a bitwise and between the first source and the complement of the second source. for i in 0..n-1 do dst[i] = src1[i] & ~src2[i]
    
    Parameters:
    
    size - register size.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - bifVVV
```
public void bifVVV(AArch64ASIMDAssembler.ASIMDSize size,
                   Register dst,
                   Register src1,
                   Register src2)
```
    C7.2.22 Bitwise insert if false.
    This instruction inserts each bit from the first source register into the destination register if the corresponding bit of the second source register is 0, otherwise leave the bit in the destination register unchanged. for i in 0..n-1 do dst[i] = src2[i] == 0 ? src1[i] : dst[i]
    
    Parameters:
    
    size - register size.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - bitVVV
```
public void bitVVV(AArch64ASIMDAssembler.ASIMDSize size,
                   Register dst,
                   Register src1,
                   Register src2)
```
    C7.2.23 Bitwise insert if true.
    This instruction inserts each bit from the first source register into the destination register if the corresponding bit of the second source register is 1, otherwise leave the bit in the destination register unchanged. for i in 0..n-1 do dst[i] = src2[i] == 1 ? src1[i] : dst[i]
    
    Parameters:
    
    size - register size.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - bslVVV
```
public void bslVVV(AArch64ASIMDAssembler.ASIMDSize size,
                   Register dst,
                   Register src1,
                   Register src2)
```
    C7.2.24 Bitwise select.
    This instruction sets each bit in the destination register to the corresponding bit from the first source register when the original destination bit was 1, otherwise from the second source register. for i in 0..n-1 do dst[i] = dst[i] == 1 ? src1[i] : src2[i]
    
    Parameters:
    
    size - register size.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - cmeqVVV
```
public void cmeqVVV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.27 Compare bitwise equal.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. for i in 0..n-1 do dst[i] = src1[i] == src2[i] ? -1 : 0
    
    Parameters:
    
    size - register size.
    
    eSize - element size. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - cmeqZeroVV
```
public void cmeqZeroVV(AArch64ASIMDAssembler.ASIMDSize size,
                       AArch64ASIMDAssembler.ElementSize eSize,
                       Register dst,
                       Register src)
```
    C7.2.28 Compare bitwise equal to zero.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. for i in 0..n-1 do dst[i] = src[i] == 0 ? -1 : 0
    
    Parameters:
    
    size - register size.
    
    eSize - element size. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src - SIMD register.
  - cmgeVVV
```
public void cmgeVVV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.29 Compare signed greater than or equal.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. for i in 0..n-1 do dst[i] = src1[i] >= src2[i] ? -1 : 0
    
    Parameters:
    
    size - register size.
    
    eSize - element size. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - cmgeZeroVV
```
public void cmgeZeroVV(AArch64ASIMDAssembler.ASIMDSize size,
                       AArch64ASIMDAssembler.ElementSize eSize,
                       Register dst,
                       Register src)
```
    C7.2.30 Compare signed greater than or equal to zero.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. for i in 0..n-1 do dst[i] >= src[i] == 0 ? -1 : 0
    
    Parameters:
    
    size - register size.
    
    eSize - element size. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src - SIMD register.
  - cmgtVVV
```
public void cmgtVVV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.31 Compare signed greater than.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. for i in 0..n-1 do dst[i] = src1[i] > src2[i] ? -1 : 0
    
    Parameters:
    
    size - register size.
    
    eSize - element size. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - cmgtZeroVV
```
public void cmgtZeroVV(AArch64ASIMDAssembler.ASIMDSize size,
                       AArch64ASIMDAssembler.ElementSize eSize,
                       Register dst,
                       Register src)
```
    C7.2.32 Compare signed greater than zero.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. for i in 0..n-1 do dst[i] = src[i] > 0 ? -1 : 0
    
    Parameters:
    
    size - register size.
    
    eSize - element size. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src - SIMD register.
  - cmhiVVV
```
public void cmhiVVV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.33 Compare unsigned higher.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. for i in 0..n-1 do dst[i] = unsigned(src1[i]) > unsigned(src2[i]) ? -1 : 0
    
    Parameters:
    
    size - register size.
    
    eSize - element size. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - cmhsVVV
```
public void cmhsVVV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.34 Compare unsigned higher or same.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. for i in 0..n-1 do dst[i] = unsigned(src1[i]) >= unsigned(src2[i]) ? -1 : 0
    
    Parameters:
    
    size - register size.
    
    eSize - element size. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - cmleZeroVV
```
public void cmleZeroVV(AArch64ASIMDAssembler.ASIMDSize size,
                       AArch64ASIMDAssembler.ElementSize eSize,
                       Register dst,
                       Register src)
```
    C7.2.35 Compare signed less than or equal to zero.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. for i in 0..n-1 do dst[i] = src[i] <= 0 ? -1 : 0
    
    Parameters:
    
    size - register size.
    
    eSize - element size. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src - SIMD register.
  - cmltZeroVV
```
public void cmltZeroVV(AArch64ASIMDAssembler.ASIMDSize size,
                       AArch64ASIMDAssembler.ElementSize eSize,
                       Register dst,
                       Register src)
```
    C7.2.36 Compare signed less than zero.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. for i in 0..n-1 do dst[i] = src[i] < 0 ? -1 : 0
    
    Parameters:
    
    size - register size.
    
    eSize - element size. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src - SIMD register.
  - cmtstVVV
```
public void cmtstVVV(AArch64ASIMDAssembler.ASIMDSize size,
                     AArch64ASIMDAssembler.ElementSize eSize,
                     Register dst,
                     Register src1,
                     Register src2)
```
    C7.2.37 Compare bitwise test bits nonzero.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. for i in 0..n-1 do dst[i] = (src1[i] & src2[i]) == 0 ? 0 : -1
    
    Parameters:
    
    size - register size.
    
    eSize - element size. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - cntVV
```
public void cntVV(AArch64ASIMDAssembler.ASIMDSize size,
                  Register dst,
                  Register src)
```
    C7.2.38 Population Count per byte.
    dst[0...n] = countBitCountOfEachByte(src[0...n]), n = size/8.
    
    Parameters:
    
    size - register size.
    
    dst - SIMD register. Should not be null.
    
    src - SIMD register. Should not be null.
  - dupSX
```
public void dupSX(AArch64ASIMDAssembler.ElementSize eSize,
                  Register dst,
                  Register src,
                  int index)
```
    C7.2.39 Duplicate vector element to scalar.
    Note that, regardless of the source vector element's index, the value is always copied into the beginning of the destination register (offset 0). dst[0] = src[index]
    
    Parameters:
    
    eSize - size of value to duplicate.
    
    dst - SIMD register
    
    src - SIMD register
    
    index - offset of value to duplicate
  - dupVX
```
public void dupVX(AArch64ASIMDAssembler.ASIMDSize dstSize,
                  AArch64ASIMDAssembler.ElementSize eSize,
                  Register dst,
                  Register src,
                  int index)
```
    C7.2.39 Duplicate vector element to vector.
    dst[0..n-1] = src[index]{n}
    
    Parameters:
    
    dstSize - total size of all duplicates.
    
    eSize - size of value to duplicate.
    
    dst - SIMD register.
    
    src - SIMD register.
    
    index - offset of value to duplicate
  - dupVG
```
public void dupVG(AArch64ASIMDAssembler.ASIMDSize dstSize,
                  AArch64ASIMDAssembler.ElementSize eSize,
                  Register dst,
                  Register src)
```
    C7.2.40 Duplicate general-purpose register to vector.
    dst(simd) = src(gp){n}
    
    Parameters:
    
    dstSize - total size of all duplicates.
    
    eSize - size of value to duplicate.
    
    dst - SIMD register.
    
    src - general-purpose register.
  - eorVVV
```
public void eorVVV(AArch64ASIMDAssembler.ASIMDSize size,
                   Register dst,
                   Register src1,
                   Register src2)
```
    C7.2.41 Bitwise exclusive or vector.
    for i in 0..n-1 do dst[i] = src1[i] ^ src2[i]
    
    Parameters:
    
    size - register size.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - extVVV
```
public void extVVV(AArch64ASIMDAssembler.ASIMDSize size,
                   Register dst,
                   Register src1,
                   Register src2,
                   int src1LowIdx)
```
    C7.2.43 Extract from pair of vectors.
    
    From the manual: "This instruction extracts the lowest vector elements from the second source SIMD&FP register and the highest vector elements from the first source SIMD&FP register, concatenates the results into a vector, and writes the vector to the destination SIMD&FP register vector. The index value specifies the lowest vector element to extract from the first source register, and consecutive elements are extracted from the first, then second, source registers until the destination vector is filled." For this operation, vector elements are always byte sized.
    
    Parameters:
    
    size - operation size.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
    
    src1LowIdx - The lowest index of the first source registers to extract
  - fabsVV
```
public void fabsVV(AArch64ASIMDAssembler.ASIMDSize size,
                   AArch64ASIMDAssembler.ElementSize eSize,
                   Register dst,
                   Register src)
```
    C7.2.45 Floating-point absolute value.
    for i in 0..n-1 do dst[i] = fp_abs(src[i])
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord. Note ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src - SIMD register.
  - facgeVVV
```
public void facgeVVV(AArch64ASIMDAssembler.ASIMDSize size,
                     AArch64ASIMDAssembler.ElementSize eSize,
                     Register dst,
                     Register src1,
                     Register src2)
```
    C7.2.47 Floating-point absolute compare greater than or equal.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. for i in 0..n-1 do dst[i] = fp_abs(src1[i]) >= fp_abs(src2[i]) ? -1 : 0
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - facgtVVV
```
public void facgtVVV(AArch64ASIMDAssembler.ASIMDSize size,
                     AArch64ASIMDAssembler.ElementSize eSize,
                     Register dst,
                     Register src1,
                     Register src2)
```
    C7.2.48 Floating-point absolute compare greater than.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. for i in 0..n-1 do dst[i] = fp_abs(src1[i]) > fp_abs(src2[i]) ? -1 : 0
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - facgtSSS
```
public void facgtSSS(AArch64ASIMDAssembler.ElementSize eSize,
                     Register dst,
                     Register src1,
                     Register src2)
```
    C7.2.48 Floating-point absolute compare greater than.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. dst = fp_abs(src1) > fp_abs(src2) > -1 : 0
    
    Parameters:
    
    eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - faddVVV
```
public void faddVVV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.49 floating point add vector.
    for i in 0..n-1 do dst[i] = fp_add(src1[i], src2[i])
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord. Note ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - fcmeqVVV
```
public void fcmeqVVV(AArch64ASIMDAssembler.ASIMDSize size,
                     AArch64ASIMDAssembler.ElementSize eSize,
                     Register dst,
                     Register src1,
                     Register src2)
```
    C7.2.56 Floating-point compare equal.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. for i in 0..n-1 do dst[i] = src1[i] == src2[i] ? -1 : 0
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - fcmeqZeroVV
```
public void fcmeqZeroVV(AArch64ASIMDAssembler.ASIMDSize size,
                        AArch64ASIMDAssembler.ElementSize eSize,
                        Register dst,
                        Register src)
```
    C7.2.57 Floating-point compare equal to zero.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. for i in 0..n-1 do dst[i] = src[i] == 0 ? -1 : 0
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src - SIMD register.
  - fcmgeVVV
```
public void fcmgeVVV(AArch64ASIMDAssembler.ASIMDSize size,
                     AArch64ASIMDAssembler.ElementSize eSize,
                     Register dst,
                     Register src1,
                     Register src2)
```
    C7.2.58 Floating-point compare greater than or equal.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. for i in 0..n-1 do dst[i] = src1[i] >= src2[i] ? -1 : 0
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - fcmgeZeroVV
```
public void fcmgeZeroVV(AArch64ASIMDAssembler.ASIMDSize size,
                        AArch64ASIMDAssembler.ElementSize eSize,
                        Register dst,
                        Register src)
```
    C7.2.59 Floating-point compare greater than or equal to zero.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. for i in 0..n-1 do dst[i] >= src[i] == 0 ? -1 : 0
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src - SIMD register.
  - fcmgtVVV
```
public void fcmgtVVV(AArch64ASIMDAssembler.ASIMDSize size,
                     AArch64ASIMDAssembler.ElementSize eSize,
                     Register dst,
                     Register src1,
                     Register src2)
```
    C7.2.60 Floating-point compare greater than.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. for i in 0..n-1 do dst[i] = src1[i] > src2[i] ? -1 : 0
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - fcmgtZeroVV
```
public void fcmgtZeroVV(AArch64ASIMDAssembler.ASIMDSize size,
                        AArch64ASIMDAssembler.ElementSize eSize,
                        Register dst,
                        Register src)
```
    C7.2.61 Floating-point compare greater than zero.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. for i in 0..n-1 do dst[i] > src[i] == 0 ? -1 : 0
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src - SIMD register.
  - fcmleZeroVV
```
public void fcmleZeroVV(AArch64ASIMDAssembler.ASIMDSize size,
                        AArch64ASIMDAssembler.ElementSize eSize,
                        Register dst,
                        Register src)
```
    C7.2.64 Floating-point compare less than or equal to zero.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. for i in 0..n-1 do dst[i] <= src[i] == 0 ? -1 : 0
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src - SIMD register.
  - fcmltZeroVV
```
public void fcmltZeroVV(AArch64ASIMDAssembler.ASIMDSize size,
                        AArch64ASIMDAssembler.ElementSize eSize,
                        Register dst,
                        Register src)
```
    C7.2.65 Floating-point compare less than zero.
    
    For elements which the comparison is true, all bits of the corresponding dst lane are set to 1. Otherwise, if the comparison is false, then the corresponding dst lane is cleared. for i in 0..n-1 do dst[i] < src[i] == 0 ? -1 : 0
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src - SIMD register.
  - fcvtlVV
```
public void fcvtlVV(AArch64ASIMDAssembler.ElementSize srcESize,
                    Register dst,
                    Register src)
```
    C7.2.74 Floating-point convert to higher precision long.
    
    Parameters:
    
    srcESize - source element size. Must be ElementSize.HalfWord or ElementSize.Word. The destination element size will be double this width.
    
    dst - SIMD register.
    
    src - SIMD register.
  - fcvtnVV
```
public void fcvtnVV(AArch64ASIMDAssembler.ElementSize srcESize,
                    Register dst,
                    Register src)
```
    C7.2.79 Floating-point convert to lower precision narrow.
    
    Parameters:
    
    srcESize - source element size. Must be ElementSize.Word or ElementSize.DoubleWord. The destination element size will be half this width.
    
    dst - SIMD register.
    
    src - SIMD register.
  - fcvtzsVV
```
public void fcvtzsVV(AArch64ASIMDAssembler.ASIMDSize size,
                     AArch64ASIMDAssembler.ElementSize eSize,
                     Register dst,
                     Register src)
```
    C7.2.90 Floating-point convert to to signed integer, rounding toward zero.
    
    Parameters:
    
    size - register size.
    
    eSize - source element size. Must be ElementSize.Word or ElementSize.DoubleWord. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src - SIMD register.
  - fdivVVV
```
public void fdivVVV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.97 floating point divide vector.
    for i in 0..n-1 do dst[i] = fp_div(src1[i], src2[i])
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord. Note ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - fmaxVVV
```
public void fmaxVVV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.101 floating-point maximum.
    for i in 0..n-1 do dst[i] = fp_max(src1[i], src2[i])
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord. Note ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - fminVVV
```
public void fminVVV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.111 floating-point minimum.
    for i in 0..n-1 do dst[i] = fp_min(src1[i], src2[i])
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord. Note ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - fmlaVVV
```
public void fmlaVVV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.122 Floating-point fused multiply-add to accumulator.
    for i in 0..n-1 do dst[i] += fp_multiply(src1[i], src2[i])
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord. Note ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - fmlsVVV
```
public void fmlsVVV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.126 Floating-point fused multiply-subtract from accumulator.
    for i in 0..n-1 do dst[i] -= fp_multiply(src1[i], src2[i])
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord. Note ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - fmovVI
```
public void fmovVI(AArch64ASIMDAssembler.ASIMDSize size,
                   AArch64ASIMDAssembler.ElementSize eSize,
                   Register dst,
                   long imm64)
```
    C7.2.132 Floating-point move immediate.
    dst = imm64{1,2}
    
    Parameters:
    
    size - register size.
    
    dst - SIMD register.
    
    imm64 - 64-bit value to move. Is copied twice if register size is 128.
  - fmulVVV
```
public void fmulVVV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.135 floating point multiply vector.
    for i in 0..n-1 do dst[i] = fp_mul(src1[i], src2[i])
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord. Note ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - fnegVV
```
public void fnegVV(AArch64ASIMDAssembler.ASIMDSize size,
                   AArch64ASIMDAssembler.ElementSize eSize,
                   Register dst,
                   Register src)
```
    C7.2.139 Floating-point negate.
    for i in 0..n-1 do dst[i] = -src[i]
    
    Parameters:
    
    size - register size.
    
    eSize - source element size. Must be ElementSize.Word or ElementSize.DoubleWord. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src - SIMD register.
  - fsqrtVV
```
public void fsqrtVV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src)
```
    C7.2.171 Floating-point square root.
    for i in 0..n-1 do dst[i] = fp_sqrt(src[i])
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord. Note ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src - SIMD register.
  - fsubVVV
```
public void fsubVVV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.173 floating point subtract vector.
    for i in 0..n-1 do dst[i] = fp_sub(src1[i], src2[i])
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord. Note ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - insXG
```
public void insXG(AArch64ASIMDAssembler.ElementSize eSize,
                  Register dst,
                  int index,
                  Register src)
```
    C7.2.176 Insert vector element from general-purpose register.
    dst[index] = src Note the rest of the dst register is unaltered.
    
    Parameters:
    
    eSize - size of value to duplicate.
    
    dst - SIMD register.
    
    index - offset of value to duplicate
    
    src - SIMD register.
  - ld1MultipleV
```
public void ld1MultipleV(AArch64ASIMDAssembler.ASIMDSize size,
                         AArch64ASIMDAssembler.ElementSize eSize,
                         Register dst,
                         AArch64Address addr)
```
    C7.2.177 Load multiple single-element structures to one register.
    This instruction loads multiple single-element structures from memory and writes the result to one register.
    
    Parameters:
    
    size - register size.
    
    eSize - element size.
    
    dst - destination of first structure's value
    
    addr - address of first structure.
  - ld1MultipleVV
```
public void ld1MultipleVV(AArch64ASIMDAssembler.ASIMDSize size,
                          AArch64ASIMDAssembler.ElementSize eSize,
                          Register dst1,
                          Register dst2,
                          AArch64Address addr)
```
    C7.2.177 Load multiple single-element structures to two registers.
    This instruction loads multiple single-element structures from memory and writes the result to two registers. Note the two registers must be consecutive (modulo the number of SIMD registers).
    
    Parameters:
    
    size - register size.
    
    eSize - element size.
    
    dst1 - destination of first structure's value.
    
    dst2 - destination of second structure's value. Must be register after dst1.
    
    addr - address of first structure.
  - ld1MultipleVVV
```
public void ld1MultipleVVV(AArch64ASIMDAssembler.ASIMDSize size,
                           AArch64ASIMDAssembler.ElementSize eSize,
                           Register dst1,
                           Register dst2,
                           Register dst3,
                           AArch64Address addr)
```
    C7.2.177 Load multiple single-element structures to three registers.
    This instruction loads multiple single-element structures from memory and writes the result to three registers. Note the three registers must be consecutive (modulo the number of SIMD registers).
    
    Parameters:
    
    size - register size.
    
    eSize - element size.
    
    dst1 - destination of first structure's value.
    
    dst2 - destination of second structure's value. Must be register after dst1.
    
    dst3 - destination of third structure's value. Must be register after dst2.
    
    addr - address of first structure.
  - ld1MultipleVVVV
```
public void ld1MultipleVVVV(AArch64ASIMDAssembler.ASIMDSize size,
                            AArch64ASIMDAssembler.ElementSize eSize,
                            Register dst1,
                            Register dst2,
                            Register dst3,
                            Register dst4,
                            AArch64Address addr)
```
    C7.2.177 Load multiple single-element structures to four registers.
    This instruction loads multiple single-element structures from memory and writes the result to four registers. Note the four registers must be consecutive (modulo the number of SIMD registers).
    
    Parameters:
    
    size - register size.
    
    eSize - element size.
    
    dst1 - destination of first structure's value.
    
    dst2 - destination of second structure's value. Must be register after dst1.
    
    dst3 - destination of third structure's value. Must be register after dst2.
    
    dst4 - destination of fourth structure's value. Must be register after dst3.
    
    addr - address of first structure.
  - ld1rV
```
public void ld1rV(AArch64ASIMDAssembler.ASIMDSize size,
                  AArch64ASIMDAssembler.ElementSize eSize,
                  Register dst,
                  AArch64Address addr)
```
    C7.2.179 Load one single-element structure and replicate to all lanes (of one register).
    This instruction loads a single-element structure from memory and replicates the structure to all lanes of the register.
    
    Parameters:
    
    size - register size.
    
    eSize - element size of value to replicate.
    
    dst - SIMD register.
    
    addr - address of structure.
  - mlaVVV
```
public void mlaVVV(AArch64ASIMDAssembler.ASIMDSize size,
                   AArch64ASIMDAssembler.ElementSize eSize,
                   Register dst,
                   Register src1,
                   Register src2)
```
    C7.2.196 Multiply-add to accumulator.
    for i in 0..n-1 do dst[i] += int_multiply(src1[i], src2[i])
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Cannot be ElementSize.DoubleWord.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - mlsVVV
```
public void mlsVVV(AArch64ASIMDAssembler.ASIMDSize size,
                   AArch64ASIMDAssembler.ElementSize eSize,
                   Register dst,
                   Register src1,
                   Register src2)
```
    C7.2.198 Multiply-subtract from accumulator.
    for i in 0..n-1 do dst[i] -= int_multiply(src1[i], src2[i])
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Cannot be ElementSize.DoubleWord.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - moviVI
```
public void moviVI(AArch64ASIMDAssembler.ASIMDSize size,
                   Register dst,
                   long imm)
```
    C7.2.204 Move immediate.
    dst = imm{1,2}
    
    Parameters:
    
    size - register size.
    
    dst - SIMD register.
    
    imm - long value to move. If size is 128, then this value is copied twice
  - mulVVV
```
public void mulVVV(AArch64ASIMDAssembler.ASIMDSize size,
                   AArch64ASIMDAssembler.ElementSize eSize,
                   Register dst,
                   Register src1,
                   Register src2)
```
    C7.2.206 Integer multiply vector.
    for i in 0..n-1 do dst[i] = int_mul(src1[i], src2[i])
    
    Parameters:
    
    size - register size.
    
    eSize - element size. Cannot be ElementSize.DoubleWord.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - mvniVI
```
public void mvniVI(AArch64ASIMDAssembler.ASIMDSize size,
                   Register dst,
                   long imm)
```
    C7.2.208 Move inverted immediate.
    dst = ~(imm{1,2})
    
    Parameters:
    
    size - register size.
    
    dst - SIMD register.
    
    imm - long value to move. If size is 128, then this value is copied twice
  - negVV
```
public void negVV(AArch64ASIMDAssembler.ASIMDSize size,
                  AArch64ASIMDAssembler.ElementSize eSize,
                  Register dst,
                  Register src)
```
    C7.2.209 Negate.
    for i in 0..n-1 do dst[i] = -src[i]
    
    Parameters:
    
    size - register size.
    
    eSize - source element size. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src - SIMD register.
  - notVV
```
public void notVV(AArch64ASIMDAssembler.ASIMDSize size,
                  Register dst,
                  Register src)
```
    C7.2.210 Bitwise not vector.
    for i in 0..n-1 do dst[i] = ~src[i]
    
    Parameters:
    
    size - register size.
    
    dst - SIMD register.
    
    src - SIMD register.
  - ornVVV
```
public void ornVVV(AArch64ASIMDAssembler.ASIMDSize size,
                   Register dst,
                   Register src1,
                   Register src2)
```
    C7.2.211 Bitwise inclusive or not vector.
    for i in 0..n-1 do dst[i] = src1[i] | ~src2[i]
    
    Parameters:
    
    size - register size.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - orrVI
```
public void orrVI(AArch64ASIMDAssembler.ASIMDSize size,
                  Register dst,
                  long imm)
```
    C7.2.212 Bitwise inclusive or.
    dst = dst | imm{1,2}
    
    Parameters:
    
    size - register size.
    
    dst - SIMD register.
    
    imm - long value to move. If size is 128, then this value is copied twice
  - orrVVV
```
public void orrVVV(AArch64ASIMDAssembler.ASIMDSize size,
                   Register dst,
                   Register src1,
                   Register src2)
```
    C7.2.213 Bitwise inclusive or vector.
    for i in 0..n-1 do dst[i] = src1[i] | src2[i]
    
    Parameters:
    
    size - register size.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - rev16VV
```
public void rev16VV(AArch64ASIMDAssembler.ASIMDSize size,
                    Register dst,
                    Register src)
```
    C7.2.219 Reverse elements in 16-bit halfwords.
    This instruction reverses the order of 8-bit elements in each halfword.
    
    Parameters:
    
    size - register size.
    
    dst - SIMD register.
    
    src - SIMD register.
  - rev32VV
```
public void rev32VV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize revGranularity,
                    Register dst,
                    Register src)
```
    C7.2.220 Reverse elements in 32-bit words.
    This instruction reverses the order of elements of size revGranularity in each 32-bit word.
    
    Parameters:
    
    size - register size.
    
    revGranularity - within each element at what granularity the bits should be reversed. Can be of size Byte of HalfWord
    
    dst - SIMD register.
    
    src - SIMD register.
  - rev64VV
```
public void rev64VV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize revGranularity,
                    Register dst,
                    Register src)
```
    C7.2.221 Reverse elements in 64-bit words.
    This instruction reverses the order of elements of size revGranularity in each 64-bit word.
    
    Parameters:
    
    size - register size.
    
    revGranularity - within each element at what granularity the bits should be reversed. DoubleWord is not allowed.
    
    dst - SIMD register.
    
    src - SIMD register.
  - saddlvSV
```
public void saddlvSV(AArch64ASIMDAssembler.ASIMDSize size,
                     AArch64ASIMDAssembler.ElementSize elementSize,
                     Register dst,
                     Register src)
```
    C7.2.231 Signed add across long vector.
    dst = src[0] + ....+ src[n].
    
    Dst is twice the width of the vector elements, so overflow is not possible.
    
    Parameters:
    
    size - register size.
    
    elementSize - Unexpanded width of each addition operand.
    
    dst - SIMD register. Should not be null.
    
    src - SIMD register. Should not be null.
  - scvtfVV
```
public void scvtfVV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src)
```
    C7.2.234 Signed integer convert to floating-point.
    
    Parameters:
    
    size - register size.
    
    eSize - source element size. Must be ElementSize.Word or ElementSize.DoubleWord. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src - SIMD register.
  - shlVVI
```
public void shlVVI(AArch64ASIMDAssembler.ASIMDSize size,
                   AArch64ASIMDAssembler.ElementSize eSize,
                   Register dst,
                   Register src,
                   int shiftAmt)
```
    C7.2.254 shift left (immediate).
    for i in 0..n-1 do dst[i] = src[i] << imm
    
    Parameters:
    
    size - register size.
    
    eSize - element size. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src - SIMD register.
    
    shiftAmt - shift amount.
  - smaxVVV
```
public void smaxVVV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.268 Signed maximum.
    for i in 0..n-1 do dst[i] = int_max(src1[i], src2[i])
    
    Parameters:
    
    size - register size.
    
    eSize - element size.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - sminVVV
```
public void sminVVV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.271 Signed minimum.
    for i in 0..n-1 do dst[i] = int_min(src1[i], src2[i])
    
    Parameters:
    
    size - register size.
    
    eSize - element size.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - smlalVVV
```
public void smlalVVV(AArch64ASIMDAssembler.ElementSize srcESize,
                     Register dst,
                     Register src1,
                     Register src2)
```
    C7.2.275 Signed Multiply-Add Long.
    for i in 0..n-1 do dst[i] += int_multiply(src1[i], src2[i])
    
    Parameters:
    
    srcESize - source element size. Cannot be ElementSize.DoubleWord. The destination element size will be double this width.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - smlslVVV
```
public void smlslVVV(AArch64ASIMDAssembler.ElementSize srcESize,
                     Register dst,
                     Register src1,
                     Register src2)
```
    C7.2.277 Signed Multiply-Subtract Long.
    for i in 0..n-1 do dst[i] -= int_multiply(src1[i], src2[i])
    
    Parameters:
    
    srcESize - source element size. Cannot be ElementSize.DoubleWord. The destination element size will be double this width.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - smovGX
```
public void smovGX(AArch64ASIMDAssembler.ElementSize dstESize,
                   AArch64ASIMDAssembler.ElementSize srcESize,
                   Register dst,
                   Register src,
                   int index)
```
    C7.2.279 Signed move vector element to general-purpose register.
    dst (gp) = sign-extend(src[index]) (simd).
    Note that the target register size (dst) must be greater than the source element size.
    
    Parameters:
    
    dstESize - width of sign-extended.
    
    srcESize - width of element to move.
    
    dst - general-purpose register.
    
    src - SIMD register.
    
    index - offset of value to move.
  - sshlVVV
```
public void sshlVVV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.315 signed shift left (register).
    for i in 0..n-1 do if(byte(src2[i] > 0 dst[i] = (src1[i] << byte(src2[i] else dst[i] = (src1[i] >> byte(src2[i])
    
    Parameters:
    
    size - register size.
    
    eSize - element size. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - sshllVVI
```
public void sshllVVI(AArch64ASIMDAssembler.ElementSize srcESize,
                     Register dst,
                     Register src,
                     int shiftAmt)
```
    C7.2.316 Signed shift left long (immediate).
    
    From the manual: "This instruction reads each vector element from the source SIMD&FP register, left shifts each vector element by the specified shift amount ... The destination vector elements are twice as long as the source vector elements. All the values in this instruction are signed integer values."
    
    Parameters:
    
    srcESize - source element size. Cannot be ElementSize.DoubleWord. The destination element size will be double this width.
    
    dst - SIMD register.
    
    src - SIMD register.
    
    shiftAmt - shift left amount.
  - sshrVVI
```
public void sshrVVI(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src,
                    int shiftAmt)
```
    C7.2.317 signed shift right (immediate).
    for i in 0..n-1 do dst[i] = src[i] >> imm
    
    Parameters:
    
    size - register size.
    
    eSize - element size. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src - SIMD register.
    
    shiftAmt - shift right amount.
  - st1MultipleV
```
public void st1MultipleV(AArch64ASIMDAssembler.ASIMDSize size,
                         AArch64ASIMDAssembler.ElementSize eSize,
                         Register src,
                         AArch64Address addr)
```
    C7.2.321 Store multiple single-element structures from one register.
    This instruction stores elements to memory from one register.
    
    Parameters:
    
    size - register size.
    
    eSize - element size.
    
    src - value to store in structure.
    
    addr - address of first structure.
  - st1MultipleVV
```
public void st1MultipleVV(AArch64ASIMDAssembler.ASIMDSize size,
                          AArch64ASIMDAssembler.ElementSize eSize,
                          Register src1,
                          Register src2,
                          AArch64Address addr)
```
    C7.2.321 Store multiple single-element structures from two registers.
    This instruction stores elements to memory from two registers. Note the two registers must be consecutive (modulo the number of SIMD registers).
    
    Parameters:
    
    size - register size.
    
    eSize - element size.
    
    src1 - value to store in first structure.
    
    src2 - value to store in second structure. Must be register after src1.
    
    addr - address of first structure.
  - st1MultipleVVV
```
public void st1MultipleVVV(AArch64ASIMDAssembler.ASIMDSize size,
                           AArch64ASIMDAssembler.ElementSize eSize,
                           Register src1,
                           Register src2,
                           Register src3,
                           AArch64Address addr)
```
    C7.2.321 Store multiple single-element structures from three registers.
    This instruction stores elements to memory from three registers. Note the three registers must be consecutive (modulo the number of SIMD registers).
    
    Parameters:
    
    size - register size.
    
    eSize - element size.
    
    src1 - value to store in first structure.
    
    src2 - value to store in second structure. Must be register after src1.
    
    src3 - value to store in third structure. Must be register after src2.
    
    addr - address of first structure.
  - st1MultipleVVVV
```
public void st1MultipleVVVV(AArch64ASIMDAssembler.ASIMDSize size,
                            AArch64ASIMDAssembler.ElementSize eSize,
                            Register src1,
                            Register src2,
                            Register src3,
                            Register src4,
                            AArch64Address addr)
```
    C7.2.321 Store multiple single-element structures from four registers.
    This instruction stores elements to memory from four registers. Note the four registers must be consecutive (modulo the number of SIMD registers).
    
    Parameters:
    
    size - register size.
    
    eSize - element size.
    
    src1 - value to store in first structure.
    
    src2 - value to store in second structure. Must be register after src1.
    
    src3 - value to store in third structure. Must be register after src2.
    
    src4 - value to store in fourth structure. Must be register after src3.
    
    addr - address of first structure.
  - subSSS
```
public void subSSS(AArch64ASIMDAssembler.ElementSize eSize,
                   Register dst,
                   Register src1,
                   Register src2)
```
    C7.2.334 Integer subtract scalar.
    dst[0] = int_sub(src1[0], src2[0])
    Note that only 64-bit (DoubleWord) operations are available.
    
    Parameters:
    
    eSize - element size. Must be of type ElementSize.DoubleWord
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - subVVV
```
public void subVVV(AArch64ASIMDAssembler.ASIMDSize size,
                   AArch64ASIMDAssembler.ElementSize eSize,
                   Register dst,
                   Register src1,
                   Register src2)
```
    C7.2.334 Integer subtract vector.
    for i in 0..n-1 do dst[i] = int_sub(src1[i], src2[i])
    
    Parameters:
    
    size - register size.
    
    eSize - element size.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - tblVVV
```
public void tblVVV(AArch64ASIMDAssembler.ASIMDSize size,
                   Register dst,
                   Register table,
                   Register index)
```
    C7.2.339 Table vector lookup (single register table variant).
    This instruction is used to perform permutations at a byte granularity. Within the destination, each byte is determined by using the index register to pick either a value within the table register, or if the index exceeds the table's boundary, then the dst register is set to zero.
```
 tbl[0..n-1] = table[0..n-1]
 for i in 0..n-1 {
     idx = index[i]
     if (index < n)
      dst[i] = tbl[idx]
     else
      dst[i] = 0
 }
 
```
    Parameters:
    
    size - register size.
    
    dst - SIMD register.
    
    table - SIMD register.
    
    index - SIMD register.
  - tblVVVV
```
public void tblVVVV(AArch64ASIMDAssembler.ASIMDSize size,
                    Register dst,
                    Register table1,
                    Register table2,
                    Register index)
```
    C7.2.339 Table vector lookup (two register table variant).
    This instruction is used to perform permutations at a byte granularity. A table is formed by combining the two table registers. Within the destination, each byte is determined by using the index register to pick either a value within the table, or if the index exceeds the table's boundary, then the dst register is set to 0.
```
 tbl[0..n-1] = table1[0..n-1]
 tbl[n..2n-1] = table2[0..n-1]
 for i in 0..n-1 {
     idx = index[i]
     if (index < 2n)
      dst[i] = tbl[idx]
     else
      dst[i] = 0
 }
 
```
    Parameters:
    
    size - register size.
    
    dst - SIMD register.
    
    table1 - SIMD register.
    
    table2 - SIMD register.
    
    index - SIMD register.
  - tbxVVV
```
public void tbxVVV(AArch64ASIMDAssembler.ASIMDSize size,
                   Register dst,
                   Register table,
                   Register index)
```
    C7.2.440 Table vector lookup extension (single register table variant).
    This instruction is used to perform permutations at a byte granularity. Within the destination, each byte is determined by using the index register to pick either a value within the table register, or if the index exceeds the table's boundary, then the dst register is unchanged.
```
 tbl[0..n-1] = table[0..n-1]
 for i in 0..n-1 {
     idx = index[i]
     if (index < n)
      dst[i] = tbl[idx]
 }
 
```
    Parameters:
    
    size - register size.
    
    dst - SIMD register.
    
    table - SIMD register.
    
    index - SIMD register.
  - trn1VVV
```
public void trn1VVV(AArch64ASIMDAssembler.ASIMDSize dstSize,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.341 Transpose vectors (primary).
    From the manual: "This instructions reads corresponding even-numbered vector elements from the two registers, starting at zero, [and] places each result into consecutive elements of a vector."
    
    Parameters:
    
    dstSize - register size of destination register. Note only half of this size will be used within the source registers.
    
    eSize - element size.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - trn2VVV
```
public void trn2VVV(AArch64ASIMDAssembler.ASIMDSize dstSize,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.342 Transpose vectors (secondary).
    From the manual: "This instructions reads corresponding odd-numbered vector elements from the two registers, starting at zero, [and] places each result into consecutive elements of a vector."
    
    Parameters:
    
    dstSize - register size of destination register. Note only half of this size will be used within the source registers.
    
    eSize - element size.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - uaddlvSV
```
public void uaddlvSV(AArch64ASIMDAssembler.ASIMDSize size,
                     AArch64ASIMDAssembler.ElementSize elementSize,
                     Register dst,
                     Register src)
```
    C7.2.350 Unsigned add across long vector.
    dst = src[0] + ....+ src[n].
    
    Dst is twice the width of the vector elements, so overflow is not possible.
    
    Parameters:
    
    size - register size.
    
    elementSize - Unexpanded width of each addition operand.
    
    dst - SIMD register. Should not be null.
    
    src - SIMD register. Should not be null.
  - umaxvSV
```
public void umaxvSV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize elementSize,
                    Register dst,
                    Register src)
```
    C7.2.362 Unsigned maximum across vector.
    dst = uint_max(src[0], ..., src[n]).
    
    Parameters:
    
    size - register size.
    
    elementSize - width of each operand.
    
    dst - SIMD register.
    
    src - SIMD register.
  - uminvSV
```
public void uminvSV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize elementSize,
                    Register dst,
                    Register src)
```
    C7.2.365 Unsigned minimum across vector.
    dst = uint_min(src[0], ..., src[n]).
    
    Parameters:
    
    size - register size.
    
    elementSize - width of each operand.
    
    dst - SIMD register.
    
    src - SIMD register.
  - umlalVVV
```
public void umlalVVV(AArch64ASIMDAssembler.ElementSize srcESize,
                     Register dst,
                     Register src1,
                     Register src2)
```
    C7.2.367 Unsigned Multiply-Add Long.
    for i in 0..n-1 do dst[i] += uint_multiply(src1[i], src2[i])
    
    Parameters:
    
    srcESize - source element size. Cannot be ElementSize.DoubleWord. The destination element size will be double this width.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - umlslVVV
```
public void umlslVVV(AArch64ASIMDAssembler.ElementSize srcESize,
                     Register dst,
                     Register src1,
                     Register src2)
```
    C7.2.369 Unsigned Multiply-Subtract Long.
    for i in 0..n-1 do dst[i] -= uint_multiply(src1[i], src2[i])
    
    Parameters:
    
    srcESize - source element size. Cannot be ElementSize.DoubleWord. The destination element size will be double this width.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - umovGX
```
public void umovGX(AArch64ASIMDAssembler.ElementSize eSize,
                   Register dst,
                   Register src,
                   int index)
```
    C7.2.371 Unsigned move vector element to general-purpose register.
    dst (gp) = src[index] (simd).
    
    Parameters:
    
    eSize - width of element to move.
    
    dst - general-purpose register.
    
    src - SIMD register.
    
    index - offset of value to move.
  - ushlVVV
```
public void ushlVVV(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.390 unsigned shift left (register).
    for i in 0..n-1 do if(byte(src2[i] > 0) dst[i] = (src1[i] << byte(src2[i]) else dst[i] = (src1[i] >>> byte(src2[i])
    
    Parameters:
    
    size - register size.
    
    eSize - element size. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - ushllVVI
```
public void ushllVVI(AArch64ASIMDAssembler.ElementSize srcESize,
                     Register dst,
                     Register src,
                     int shiftAmt)
```
    C7.2.391 Unsigned shift left long (immediate).
    
    From the manual: "This instruction reads each vector element in the lower half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits ... The destination vector elements are twice as long as the source vector elements."
    
    Parameters:
    
    srcESize - source element size. Cannot be ElementSize.DoubleWord. The destination element size will be double this width.
    
    dst - SIMD register.
    
    src - SIMD register.
    
    shiftAmt - shift left amount.
  - ushll2VVI
```
public void ushll2VVI(AArch64ASIMDAssembler.ElementSize srcESize,
                      Register dst,
                      Register src,
                      int shiftAmt)
```
    C7.2.391 Unsigned shift left long (immediate).
    
    From the manual: "This instruction reads each vector element in the upper half of the source SIMD&FP register, shifts the unsigned integer value left by the specified number of bits ... The destination vector elements are twice as long as the source vector elements."
    
    Parameters:
    
    srcESize - source element size. Cannot be ElementSize.DoubleWord. The destination element size will be twice this width.
    
    dst - SIMD register.
    
    src - SIMD register.
    
    shiftAmt - shift left amount.
  - ushrSSI
```
public void ushrSSI(AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src,
                    int shiftAmt)
```
    C7.2.392 unsigned shift right (immediate) scalar.
    for i in 0..n-1 do dst[i] = src[i] >>> imm
    
    Parameters:
    
    eSize - element size. Must be ElementSize.DoubleWord.
    
    dst - SIMD register.
    
    src - SIMD register.
    
    shiftAmt - shift right amount.
  - ushrVVI
```
public void ushrVVI(AArch64ASIMDAssembler.ASIMDSize size,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src,
                    int shiftAmt)
```
    C7.2.392 unsigned shift right (immediate) vector.
    dst = src >>> imm
    
    Parameters:
    
    size - register size.
    
    eSize - element size. ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).
    
    dst - SIMD register.
    
    src - SIMD register.
    
    shiftAmt - shift right amount.
  - uzp1VVV
```
public void uzp1VVV(AArch64ASIMDAssembler.ASIMDSize dstSize,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.399 Unzip vectors (primary).
    From the manual: "This instructions reads corresponding even-numbered vector elements from the two source registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector."
    
    Parameters:
    
    dstSize - register size of destination register. Note only half of this size will be used within the source registers.
    
    eSize - element size.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - uzp2VVV
```
public void uzp2VVV(AArch64ASIMDAssembler.ASIMDSize dstSize,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.400 Unzip vectors (secondary).
    From the manual: "This instructions reads corresponding odd-numbered vector elements from the two source registers, starting at zero, places the result from the first source register into consecutive elements in the lower half of a vector, and the result from the second source register into consecutive elements in the upper half of a vector."
    
    Parameters:
    
    dstSize - register size of destination register. Note only half of this size will be used within the source registers.
    
    eSize - element size.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - xtnVV
```
public void xtnVV(AArch64ASIMDAssembler.ElementSize dstESize,
                  Register dst,
                  Register src)
```
    C7.2.402 Extract narrow.
    
    From the manual: "This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, and writes into the lower half of the destination register..."
    
    Parameters:
    
    dstESize - destination element size. Cannot be ElementSize.DoubleWord. The source element size is twice this width.
    
    dst - SIMD register.
    
    src - SIMD register.
  - xtn2VV
```
public void xtn2VV(AArch64ASIMDAssembler.ElementSize dstESize,
                   Register dst,
                   Register src)
```
    C7.2.402 Extract narrow.
    
    From the manual: "This instruction reads each vector element from the source SIMD&FP register, narrows each value to half the original width, and writes into the upper half of the destination register..."
    
    Parameters:
    
    dstESize - destination element size. Cannot be ElementSize.DoubleWord. The source element size is twice this width.
    
    dst - SIMD register.
    
    src - SIMD register.
  - zip1VVV
```
public void zip1VVV(AArch64ASIMDAssembler.ASIMDSize dstSize,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.403 Zip vectors (primary).
    From the manual: "This instructions reads adjacent vector elements from the lower half of two source registers as pairs, interleaves the pairs ... and writes the vector to the destination register."
    
    Parameters:
    
    dstSize - register size of destination register. Note only half of this size will be used within the source registers.
    
    eSize - element size.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.
  - zip2VVV
```
public void zip2VVV(AArch64ASIMDAssembler.ASIMDSize dstSize,
                    AArch64ASIMDAssembler.ElementSize eSize,
                    Register dst,
                    Register src1,
                    Register src2)
```
    C7.2.404 Zip vectors (secondary).
    From the manual: "This instructions reads adjacent vector elements from the upper half of two source registers as pairs, interleaves the pairs ... and writes the vector to the destination register."
    
    Parameters:
    
    dstSize - register size of destination register. Note only half of this size will be used within the source registers.
    
    eSize - element size.
    
    dst - SIMD register.
    
    src1 - SIMD register.
    
    src2 - SIMD register.

Class AArch64ASIMDAssembler

Nested Class Summary

Constructor Summary

Method Summary

Methods inherited from class java.lang.Object

Constructor Detail

AArch64ASIMDAssembler

Method Detail

emitInt

absVV

addSSS

addVVV

addpVVV

addvSV

aesd

aese

aesimc

aesmc

andVVV

bicVI

bicVVV

bifVVV

bitVVV

bslVVV

cmeqVVV

cmeqZeroVV

cmgeVVV

cmgeZeroVV

cmgtVVV

cmgtZeroVV

cmhiVVV

cmhsVVV

cmleZeroVV

cmltZeroVV

cmtstVVV

cntVV

dupSX

dupVX

dupVG

eorVVV

extVVV

fabsVV

facgeVVV

facgtVVV

facgtSSS

faddVVV

fcmeqVVV

fcmeqZeroVV

fcmgeVVV

fcmgeZeroVV

fcmgtVVV

fcmgtZeroVV

fcmleZeroVV

fcmltZeroVV

fcvtlVV

fcvtnVV

fcvtzsVV

fdivVVV

fmaxVVV

fminVVV

fmlaVVV

fmlsVVV

fmovVI

fmulVVV

fnegVV

fsqrtVV

fsubVVV

insXG

ld1MultipleV

ld1MultipleVV

ld1MultipleVVV

ld1MultipleVVVV

ld1rV

mlaVVV

mlsVVV

moviVI

mulVVV

mvniVI

negVV

notVV