org.graalvm.compiler.asm.aarch64

Class AArch64ASIMDMacroAssembler

java.lang.Object

org.graalvm.compiler.asm.aarch64.AArch64ASIMDAssembler

org.graalvm.compiler.asm.aarch64.AArch64ASIMDMacroAssembler

public class AArch64ASIMDMacroAssembler
extends AArch64ASIMDAssembler

Nested Class Summary

Nested classes/interfaces inherited from class org.graalvm.compiler.asm.aarch64.AArch64ASIMDAssembler

AArch64ASIMDAssembler.ASIMDImmediateTable, AArch64ASIMDAssembler.ASIMDInstruction, AArch64ASIMDAssembler.ASIMDSize, AArch64ASIMDAssembler.ElementSize, AArch64ASIMDAssembler.ImmediateOp

Constructor Summary

Constructors

Constructor and Description
AArch64ASIMDMacroAssembler(AArch64MacroAssembler masm)

Method Summary

Modifier and Type	Method and Description
void	bicVI(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, long imm) Performs a bitwise bit clear with the provided immediate on each element.
void	elementRor(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src, int rorAmt) Performs right rotate on the provided register.
static boolean	isBicImmediate(AArch64ASIMDAssembler.ElementSize eSize, long imm) Checks whether a value, which will be placed in all elements, can be encoded as an immediate operand in a vector bit clear instruction.
static boolean	isMoveImmediate(AArch64ASIMDAssembler.ElementSize eSize, long imm) Checks whether a value, which will be placed in all elements, can be encoded as an immediate operand in a vector move instruction.
static boolean	isMoveImmediate(double imm) Checks whether a double, which will be placed in all elements, can be encoded as an immediate operand in a vector move instruction.
static boolean	isMoveImmediate(float imm) Checks whether a float, which will be placed in all elements, can be encoded as an immediate operand in a vector move instruction.
static boolean	isOrrImmediate(AArch64ASIMDAssembler.ElementSize eSize, long imm) Checks whether a value, which will be placed in all elements, can be encoded as an immediate operand in a vector bitwise inclusive or instruction.
void	moveFromIndex(AArch64ASIMDAssembler.ElementSize dstESize, AArch64ASIMDAssembler.ElementSize srcESize, Register dst, Register src, int index) Moves an indexed SIMD element to a floating-point or general-purpose register. dst = src[index]
void	moveVI(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, long imm) Moves an immediate value into each element of the result. for i in 0..n-1 do dst[i] = imm
void	moveVI(AArch64ASIMDAssembler.ASIMDSize size, Register dst, double imm) Moves an immediate value into each element of the result. for i in 0..n-1 do dst[i] = imm
void	moveVI(AArch64ASIMDAssembler.ASIMDSize size, Register dst, float imm) Moves an immediate value into each element of the result. for i in 0..n-1 do dst[i] = imm
void	moveVV(AArch64ASIMDAssembler.ASIMDSize size, Register dst, Register src) Moves an immediate value into each element of the result. for i in 0..n-1 do dst[i] = imm
void	mvnVV(AArch64ASIMDAssembler.ASIMDSize size, Register dst, Register src) C7.2.207 Bitwise not.
void	orrVI(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, long imm) Performs a bitwise inclusive or with the provided immediate on each element.
void	revVV(AArch64ASIMDAssembler.ASIMDSize size, AArch64ASIMDAssembler.ElementSize eSize, Register dst, Register src) Reverse the byte-order (endianess) of each element.
void	sxtlVV(AArch64ASIMDAssembler.ElementSize srcESize, Register dst, Register src) C7.2.338 Signed extend long.
void	uxtl2VV(AArch64ASIMDAssembler.ElementSize srcESize, Register dst, Register src) C7.2.398 Unsigned extend long.
void	uxtlVV(AArch64ASIMDAssembler.ElementSize srcESize, Register dst, Register src) C7.2.398 Unsigned extend long.

Methods inherited from class org.graalvm.compiler.asm.aarch64.AArch64ASIMDAssembler

absVV, addpVVV, addSSS, addvSV, addVVV, aesd, aese, aesimc, aesmc, andVVV, bicVI, bicVVV, bifVVV, bitVVV, bslVVV, cmeqVVV, cmeqZeroVV, cmgeVVV, cmgeZeroVV, cmgtVVV, cmgtZeroVV, cmhiVVV, cmhsVVV, cmleZeroVV, cmltZeroVV, cmtstVVV, cntVV, dupSX, dupVG, dupVX, emitInt, eorVVV, extVVV, fabsVV, facgeVVV, facgtSSS, facgtVVV, faddVVV, fcmeqVVV, fcmeqZeroVV, fcmgeVVV, fcmgeZeroVV, fcmgtVVV, fcmgtZeroVV, fcmleZeroVV, fcmltZeroVV, fcvtlVV, fcvtnVV, fcvtzsVV, fdivVVV, fmaxVVV, fminVVV, fmlaVVV, fmlsVVV, fmovVI, fmulVVV, fnegVV, fsqrtVV, fsubVVV, insXG, ld1MultipleV, ld1MultipleVV, ld1MultipleVVV, ld1MultipleVVVV, ld1rV, mlaVVV, mlsVVV, moviVI, mulVVV, mvniVI, negVV, notVV, ornVVV, orrVI, orrVVV, rev16VV, rev32VV, rev64VV, saddlvSV, scvtfVV, shlVVI, smaxVVV, sminVVV, smlalVVV, smlslVVV, smovGX, sshllVVI, sshlVVV, sshrVVI, st1MultipleV, st1MultipleVV, st1MultipleVVV, st1MultipleVVVV, subSSS, subVVV, tblVVV, tblVVVV, tbxVVV, trn1VVV, trn2VVV, uaddlvSV, umaxvSV, uminvSV, umlalVVV, umlslVVV, umovGX, ushll2VVI, ushllVVI, ushlVVV, ushrSSI, ushrVVI, uzp1VVV, uzp2VVV, xtn2VV, xtnVV, zip1VVV, zip2VVV

Methods inherited from class java.lang.Object

clone, equals, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait

Constructor Detail

AArch64ASIMDMacroAssembler

public AArch64ASIMDMacroAssembler(AArch64MacroAssembler masm)

Method Detail

isMoveImmediate

public static boolean isMoveImmediate(AArch64ASIMDAssembler.ElementSize eSize,
                                      long imm)

Checks whether a value, which will be placed in all elements, can be encoded as an immediate operand in a vector move instruction.

moveVI

public void moveVI(AArch64ASIMDAssembler.ASIMDSize size,
                   AArch64ASIMDAssembler.ElementSize eSize,
                   Register dst,
                   long imm)

Moves an immediate value into each element of the result.
for i in 0..n-1 do dst[i] = imm

Parameters:

size - register size.

eSize - element size. Must be ElementSize.Word or ElementSize.DoubleWord. Note ElementSize.DoubleWord is only applicable when size is 128 (i.e. the operation is performed on more than one element).

dst - SIMD register.

imm - value to copy into each element.

isMoveImmediate

public static boolean isMoveImmediate(float imm)

Checks whether a float, which will be placed in all elements, can be encoded as an immediate operand in a vector move instruction.

moveVI

public void moveVI(AArch64ASIMDAssembler.ASIMDSize size,
                   Register dst,
                   float imm)

Moves an immediate value into each element of the result.
for i in 0..n-1 do dst[i] = imm

Parameters:

size - register size.

dst - SIMD register.

imm - value to copy into each element.

isMoveImmediate

public static boolean isMoveImmediate(double imm)

Checks whether a double, which will be placed in all elements, can be encoded as an immediate operand in a vector move instruction.

moveVI

public void moveVI(AArch64ASIMDAssembler.ASIMDSize size,
                   Register dst,
                   double imm)

Moves an immediate value into each element of the result.
for i in 0..n-1 do dst[i] = imm

moveVV

public void moveVV(AArch64ASIMDAssembler.ASIMDSize size,
                   Register dst,
                   Register src)

Moves an immediate value into each element of the result.
for i in 0..n-1 do dst[i] = imm

isOrrImmediate

public static boolean isOrrImmediate(AArch64ASIMDAssembler.ElementSize eSize,
                                     long imm)

Checks whether a value, which will be placed in all elements, can be encoded as an immediate operand in a vector bitwise inclusive or instruction.

orrVI

public void orrVI(AArch64ASIMDAssembler.ASIMDSize size,
                  AArch64ASIMDAssembler.ElementSize eSize,
                  Register dst,
                  long imm)

Performs a bitwise inclusive or with the provided immediate on each element. for i in 0..n-1 do dst[i] |= imm

isBicImmediate

public static boolean isBicImmediate(AArch64ASIMDAssembler.ElementSize eSize,
                                     long imm)

Checks whether a value, which will be placed in all elements, can be encoded as an immediate operand in a vector bit clear instruction.

bicVI

public void bicVI(AArch64ASIMDAssembler.ASIMDSize size,
                  AArch64ASIMDAssembler.ElementSize eSize,
                  Register dst,
                  long imm)

Performs a bitwise bit clear with the provided immediate on each element. for i in 0..n-1 do dst[i] &^= imm

elementRor

public void elementRor(AArch64ASIMDAssembler.ASIMDSize size,
                       AArch64ASIMDAssembler.ElementSize eSize,
                       Register dst,
                       Register src,
                       int rorAmt)

Performs right rotate on the provided register.

moveFromIndex

public void moveFromIndex(AArch64ASIMDAssembler.ElementSize dstESize,
                          AArch64ASIMDAssembler.ElementSize srcESize,
                          Register dst,
                          Register src,
                          int index)

Moves an indexed SIMD element to a floating-point or general-purpose register.
dst = src[index]

Parameters:

dstESize - width of destination element.

srcESize - width of source element.

dst - Either floating-point or general-purpose register. If general-purpose, register may not be stackpointer or zero register.

src - SIMD register.

index - lane position of element to copy.

revVV

public void revVV(AArch64ASIMDAssembler.ASIMDSize size,
                  AArch64ASIMDAssembler.ElementSize eSize,
                  Register dst,
                  Register src)

Reverse the byte-order (endianess) of each element.

Parameters:

size - register size.

eSize - element size.

dst - SIMD register.

src - SIMD register.

mvnVV

public void mvnVV(AArch64ASIMDAssembler.ASIMDSize size,
                  Register dst,
                  Register src)

C7.2.207 Bitwise not.

Preferred alias for bitwise not (NOT).

Parameters:

size - register size.

dst - SIMD register.

src - SIMD register.

sxtlVV

public void sxtlVV(AArch64ASIMDAssembler.ElementSize srcESize,
                   Register dst,
                   Register src)

C7.2.338 Signed extend long.

Preferred alias for sshll when only sign-extending the vector elements.

Parameters:

srcESize - source element size. Cannot be ElementSize.DoubleWord. The destination element size will be double this width.

dst - SIMD register.

src - SIMD register.

uxtlVV

public void uxtlVV(AArch64ASIMDAssembler.ElementSize srcESize,
                   Register dst,
                   Register src)

C7.2.398 Unsigned extend long.

Preferred alias for ushll when only zero-extending the vector elements.

Parameters:

srcESize - source element size. Cannot be ElementSize.DoubleWord. The destination element size will be double this width.

dst - SIMD register.

src - SIMD register.

uxtl2VV

public void uxtl2VV(AArch64ASIMDAssembler.ElementSize srcESize,
                    Register dst,
                    Register src)

C7.2.398 Unsigned extend long.

Preferred alias for ushll2 when only zero-extending the vector elements.

Parameters:

srcESize - source element size. Cannot be ElementSize.DoubleWord. The destination element size will be double this width.

dst - SIMD register.

src - SIMD register.