org.graalvm.compiler.asm.amd64

Class AMD64BaseAssembler

java.lang.Object

org.graalvm.compiler.asm.Assembler

org.graalvm.compiler.asm.amd64.AMD64BaseAssembler

Direct Known Subclasses:

AMD64Assembler

public abstract class AMD64BaseAssembler
extends Assembler

This class implements an assembler that can encode most X86 instructions.

Nested Class Summary

Nested Classes

Modifier and Type	Class and Description
static class	AMD64BaseAssembler.AddressDisplacementAnnotation
static class	AMD64BaseAssembler.EVEXComparisonPredicate
static class	AMD64BaseAssembler.EVEXPrefixConfig Contains flag values for the EVEX prefix used in AVX-512 instructions.
protected static class	AMD64BaseAssembler.EVEXTuple EVEX-encoded instructions use a compressed displacement scheme by multiplying disp8 with a scaling factor N depending on the tuple type and the vector length.
static class	AMD64BaseAssembler.OperandDataAnnotation
static class	AMD64BaseAssembler.OperandSize The x86 operand sizes.
static class	AMD64BaseAssembler.VEXPrefixConfig

Nested classes/interfaces inherited from class org.graalvm.compiler.asm.Assembler

Assembler.CodeAnnotation, Assembler.InstructionCounter, Assembler.LabelHint

Field Summary

Fields

Modifier and Type	Field and Description
static int	DEFAULT_DISP8_SCALE
protected boolean	force4ByteNonZeroDisplacements If true, always encode non-zero address displacements in 4 bytes, even if they would fit in one byte.

Fields inherited from class org.graalvm.compiler.asm.Assembler

codePatchingAnnotationConsumer

Constructor Summary

Constructors

Constructor and Description
AMD64BaseAssembler(TargetDescription target) Constructs an assembler for the AMD64 architecture.

Method Summary

Modifier and Type	Method and Description
void	addFeatures(EnumSet<CPUFeature> newFeatures) Add a new item at the top of the feature stack.
protected void	annotatePatchingImmediate(int operandOffset, int operandSize)
protected void	emitModRM(int reg, Register rm) Emit the ModR/M byte for one register operand and an opcode extension in the R field.
protected void	emitModRM(Register reg, Register rm) Emit the ModR/M byte for two register operands.
protected void	emitOperandHelper(int reg, AMD64Address addr, int additionalInstructionSize)
protected void	emitOperandHelper(Register reg, AMD64Address addr, boolean force4Byte, int additionalInstructionSize) Emits the ModR/M byte and optionally the SIB byte for one register and one memory operand.
protected void	emitOperandHelper(Register reg, AMD64Address addr, int additionalInstructionSize)
protected void	emitOperandHelper(Register reg, AMD64Address addr, int additionalInstructionSize, int evexDisp8Scale)
protected void	emitVEX(int l, int pp, int mmmmm, int w, int rxb, int vvvv, boolean checkAVX) Low-level function to encode and emit the VEX prefix.
protected static int	encode(Register r)
protected void	evexPrefix(Register dst, Register mask, Register nds, AMD64Address src, AVXKind.AVXSize size, int pp, int mm, int w, int z, int b) Helper method for emitting EVEX prefix in the form of RRRM.
protected void	evexPrefix(Register dst, Register mask, Register nds, Register src, AVXKind.AVXSize size, int pp, int mm, int w, int z, int b) Helper method for emitting EVEX prefix in the form of RRRR.
EnumSet<CPUFeature>	getFeatures()
static int	getLFlag(AVXKind.AVXSize size)
protected static int	getRXB(Register reg, AMD64Address rm) Get RXB bits for register-memory instruction.
protected static int	getRXB(Register reg, Register rm) Get RXB bits for register-register instruction.
protected static boolean	inRC(RegisterCategory rc, Register r)
static boolean	isAVX512Register(Register reg)
boolean	isCurrentRegionFeature(CPUFeature feature) Returns true if the feature is included in the current topmost item of the feature stack.
static boolean	isVariableLengthAVX512Register(AMD64.CPUFeature l128feature, AMD64.CPUFeature l256feature, AVXKind.AVXSize size)
protected static boolean	needsRex(Register reg)
protected static boolean	needsRex(Register src, boolean srcIsByte)
protected void	prefix(AMD64Address adr, Register reg)
protected void	prefix(AMD64Address adr, Register reg, boolean byteinst)
protected void	prefix(Register reg)
protected void	prefix(Register reg, boolean byteinst)
protected void	prefix(Register dst, boolean dstIsByte, Register src, boolean srcIsByte)
protected void	prefix(Register dst, Register src)
protected void	prefixb(AMD64Address adr, Register reg)
protected void	prefixq(AMD64Address adr, Register src)
protected void	prefixq(Register reg)
protected void	prefixq(Register reg, Register rm) Creates prefix for the operands.
void	removeFeatures() Removes the topmost item from the feature stack and removes all of this item's features from AMD64BaseAssembler.getFeatures().
protected void	rexw()
void	setForce4ByteNonZeroDisplacements(boolean force4ByteNonZeroDisplacements)
protected void	simdPrefix(Register xreg, Register nds, AMD64Address adr, AMD64BaseAssembler.OperandSize size, int opcodeEscapePrefix, boolean isRexW)
protected void	simdPrefix(Register xreg, Register nds, AMD64Address adr, AMD64BaseAssembler.OperandSize size, int overriddenSizePrefix, int opcodeEscapePrefix, boolean isRexW)
protected void	simdPrefix(Register dst, Register nds, Register src, AMD64BaseAssembler.OperandSize size, int opcodeEscapePrefix, boolean isRexW)
protected void	simdPrefix(Register dst, Register nds, Register src, AMD64BaseAssembler.OperandSize size, int overriddenSizePrefix, int opcodeEscapePrefix, boolean isRexW)
boolean	supports(CPUFeature feature)
boolean	supportsCPUFeature(String name) Determines if the CPU feature denoted by name is supported.
boolean	vexPrefix(Register dst, Register nds, AMD64Address src, AVXKind.AVXSize size, int pp, int mmmmm, int w, int wEvex, boolean checkAVX, CPUFeature l128feature, CPUFeature l256feature) Emits a VEX or EVEX prefix depending on the target register length and the given feature requirements for variable-length (AMD64.CPUFeature.AVX512VL) AVX-512 instructions, where the source src operand is a memory location.
boolean	vexPrefix(Register dst, Register nds, AMD64Address src, Register opmask, AVXKind.AVXSize size, int pp, int mmmmm, int w, int wEvex, boolean checkAVX, CPUFeature l128feature, CPUFeature l256feature, int z, int b) Emits a VEX or EVEX prefix depending on the target register length and the given feature requirements for variable-length (AMD64.CPUFeature.AVX512VL) AVX-512 instructions, where the source src operand is a memory location.
boolean	vexPrefix(Register dst, Register nds, Register src, AVXKind.AVXSize size, int pp, int mmmmm, int w, int wEvex, boolean checkAVX) Emits a VEX or EVEX prefix depending on the target register length without considering variable-length (AMD64.CPUFeature.AVX512VL) AVX-512 instructions.
boolean	vexPrefix(Register dst, Register nds, Register src, AVXKind.AVXSize size, int pp, int mmmmm, int w, int wEvex, boolean checkAVX, CPUFeature l128feature, CPUFeature l256feature) Emits a VEX or EVEX prefix depending on the target register length and the given feature requirements for variable-length (AMD64.CPUFeature.AVX512VL) AVX-512 instructions.
boolean	vexPrefix(Register dst, Register nds, Register src, Register opmask, AVXKind.AVXSize size, int pp, int mmmmm, int w, int wEvex, boolean checkAVX, CPUFeature l128feature, CPUFeature l256feature, int z, int b) Emits a VEX or EVEX prefix depending on the target register length as well as the given feature requirements.

Methods inherited from class org.graalvm.compiler.asm.Assembler

align, bind, close, copy, createLabelName, emitByte, emitByte, emitInt, emitInt, emitLong, emitLong, emitShort, emitShort, emitString, emitString, emitString0, ensureUniquePC, getByte, getInstructionCounter, getInt, getMachineCodeCallDisplacementOffset, getPlaceholder, getReturnAddressSize, getShort, inlineObjects, isTargetMP, jmp, makeAddress, nameOf, patchJumpTarget, position, requestLabelHint, reset, setCodePatchingAnnotationConsumer

Methods inherited from class java.lang.Object

clone, equals, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait

Field Detail

force4ByteNonZeroDisplacements

protected boolean force4ByteNonZeroDisplacements

If true, always encode non-zero address displacements in 4 bytes, even if they would fit in one byte. The encoding of zero displacements should not be changed because we don't want to change the size of safepoint poll instructions.

DEFAULT_DISP8_SCALE

public static final int DEFAULT_DISP8_SCALE

See Also:

Constant Field Values

Constructor Detail

AMD64BaseAssembler

public AMD64BaseAssembler(TargetDescription target)

Constructs an assembler for the AMD64 architecture.

Method Detail

setForce4ByteNonZeroDisplacements

public void setForce4ByteNonZeroDisplacements(boolean force4ByteNonZeroDisplacements)

annotatePatchingImmediate

protected void annotatePatchingImmediate(int operandOffset,
                                         int operandSize)

getFeatures

public final EnumSet<CPUFeature> getFeatures()

addFeatures

public void addFeatures(EnumSet<CPUFeature> newFeatures)

Add a new item at the top of the feature stack. The new item will contain all those newFeatures that aren't already contained in AMD64BaseAssembler.getFeatures(). A feature stack item will always be added, even if none of the features are actually new.

removeFeatures

public void removeFeatures()

Removes the topmost item from the feature stack and removes all of this item's features from AMD64BaseAssembler.getFeatures().

isCurrentRegionFeature

public boolean isCurrentRegionFeature(CPUFeature feature)

Returns true if the feature is included in the current topmost item of the feature stack.

supports

public final boolean supports(CPUFeature feature)

supportsCPUFeature

public final boolean supportsCPUFeature(String name)

Determines if the CPU feature denoted by name is supported. This name based look up is for features only available in later JVMCI releases.

inRC

protected static boolean inRC(RegisterCategory rc,
                              Register r)

encode

protected static int encode(Register r)

rexw

protected final void rexw()

prefix

protected final void prefix(Register reg)

prefix

protected final void prefix(Register reg,
                            boolean byteinst)

prefixq

protected final void prefixq(Register reg)

prefix

protected final void prefix(Register dst,
                            Register src)

prefix

protected final void prefix(Register dst,
                            boolean dstIsByte,
                            Register src,
                            boolean srcIsByte)

prefixq

protected final void prefixq(Register reg,
                             Register rm)

Creates prefix for the operands. If the given operands exceed 3 bits, the 4th bit is encoded in the prefix.

needsRex

protected static boolean needsRex(Register reg)

needsRex

protected static boolean needsRex(Register src,
                                  boolean srcIsByte)

prefixb

protected void prefixb(AMD64Address adr,
                       Register reg)

prefix

protected void prefix(AMD64Address adr,
                      Register reg)

prefix

protected void prefix(AMD64Address adr,
                      Register reg,
                      boolean byteinst)

prefixq

protected void prefixq(AMD64Address adr,
                       Register src)

getRXB

protected static int getRXB(Register reg,
                            Register rm)

Get RXB bits for register-register instruction. In that encoding, ModRM.rm contains a register index. The R bit extends the ModRM.reg field and the B bit extends the ModRM.rm field. The X bit must be 0.

getRXB

protected static int getRXB(Register reg,
                            AMD64Address rm)

Get RXB bits for register-memory instruction. The R bit extends the ModRM.reg field. There are two cases for the memory operand:
ModRM.rm contains the base register: In that case, B extends the ModRM.rm field and X = 0.
There is an SIB byte: In that case, X extends SIB.index and B extends SIB.base.

emitModRM

protected final void emitModRM(int reg,
                               Register rm)

Emit the ModR/M byte for one register operand and an opcode extension in the R field.

Format: [ 11 reg r/m ]

emitModRM

protected final void emitModRM(Register reg,
                               Register rm)

Emit the ModR/M byte for two register operands.

Format: [ 11 reg r/m ]

emitOperandHelper

protected final void emitOperandHelper(Register reg,
                                       AMD64Address addr,
                                       boolean force4Byte,
                                       int additionalInstructionSize)

Emits the ModR/M byte and optionally the SIB byte for one register and one memory operand.

Parameters:

force4Byte - use 4 byte encoding for displacements that would normally fit in a byte

emitOperandHelper

protected final void emitOperandHelper(int reg,
                                       AMD64Address addr,
                                       int additionalInstructionSize)

emitOperandHelper

protected final void emitOperandHelper(Register reg,
                                       AMD64Address addr,
                                       int additionalInstructionSize)

emitOperandHelper

protected final void emitOperandHelper(Register reg,
                                       AMD64Address addr,
                                       int additionalInstructionSize,
                                       int evexDisp8Scale)

simdPrefix

protected final void simdPrefix(Register xreg,
                                Register nds,
                                AMD64Address adr,
                                AMD64BaseAssembler.OperandSize size,
                                int overriddenSizePrefix,
                                int opcodeEscapePrefix,
                                boolean isRexW)

simdPrefix

protected final void simdPrefix(Register xreg,
                                Register nds,
                                AMD64Address adr,
                                AMD64BaseAssembler.OperandSize size,
                                int opcodeEscapePrefix,
                                boolean isRexW)

simdPrefix

protected final void simdPrefix(Register dst,
                                Register nds,
                                Register src,
                                AMD64BaseAssembler.OperandSize size,
                                int overriddenSizePrefix,
                                int opcodeEscapePrefix,
                                boolean isRexW)

simdPrefix

protected final void simdPrefix(Register dst,
                                Register nds,
                                Register src,
                                AMD64BaseAssembler.OperandSize size,
                                int opcodeEscapePrefix,
                                boolean isRexW)

emitVEX

protected final void emitVEX(int l,
                             int pp,
                             int mmmmm,
                             int w,
                             int rxb,
                             int vvvv,
                             boolean checkAVX)

Low-level function to encode and emit the VEX prefix.

2 byte form: [1100 0101] [R vvvv L pp]
3 byte form: [1100 0100] [RXB m-mmmm] [W vvvv L pp]

The RXB and vvvv fields are stored in 1's complement in the prefix encoding. This function performs the 1s complement conversion, the caller is expected to pass plain unencoded arguments.

The pp field encodes an extension to the opcode:
00: no extension
01: 66
10: F3
11: F2

The m-mmmm field encodes the leading bytes of the opcode:
00001: implied 0F leading opcode byte (default in 2-byte encoding)
00010: implied 0F 38 leading opcode bytes
00011: implied 0F 3A leading opcode bytes

This function automatically chooses the 2 or 3 byte encoding, based on the XBW flags and the m-mmmm field.

getLFlag

public static int getLFlag(AVXKind.AVXSize size)

isAVX512Register

public static boolean isAVX512Register(Register reg)

isVariableLengthAVX512Register

public static boolean isVariableLengthAVX512Register(AMD64.CPUFeature l128feature,
                                                     AMD64.CPUFeature l256feature,
                                                     AVXKind.AVXSize size)

vexPrefix

public final boolean vexPrefix(Register dst,
                               Register nds,
                               Register src,
                               AVXKind.AVXSize size,
                               int pp,
                               int mmmmm,
                               int w,
                               int wEvex,
                               boolean checkAVX)

Emits a VEX or EVEX prefix depending on the target register length without considering variable-length (AMD64.CPUFeature.AVX512VL) AVX-512 instructions. No opmask register is encoded for AVX-512 instructions.

See Also:

#vexPrefix(Register, Register, Register, Register, AVXSize, int, int, int, int, boolean, CPUFeature, CPUFeature, int, int)

vexPrefix

public final boolean vexPrefix(Register dst,
                               Register nds,
                               Register src,
                               AVXKind.AVXSize size,
                               int pp,
                               int mmmmm,
                               int w,
                               int wEvex,
                               boolean checkAVX,
                               CPUFeature l128feature,
                               CPUFeature l256feature)

Emits a VEX or EVEX prefix depending on the target register length and the given feature requirements for variable-length (AMD64.CPUFeature.AVX512VL) AVX-512 instructions. Here, the z and b bits are unset (0) when emitting an EVEX prefix and no opmask register is assumed.

See Also:

#vexPrefix(Register, Register, Register, Register, AVXSize, int, int, int, int, boolean, CPUFeature, CPUFeature, int, int)

vexPrefix

public final boolean vexPrefix(Register dst,
                               Register nds,
                               Register src,
                               Register opmask,
                               AVXKind.AVXSize size,
                               int pp,
                               int mmmmm,
                               int w,
                               int wEvex,
                               boolean checkAVX,
                               CPUFeature l128feature,
                               CPUFeature l256feature,
                               int z,
                               int b)

Emits a VEX or EVEX prefix depending on the target register length as well as the given feature requirements. If the requirements indicate that a variable-length (AMD64.CPUFeature.AVX512VL) variant of the target instruction exists, an EVEX prefix is emitted. l128feature denotes the requirements if the target register side (size) is AVXKind.AVXSize.XMM and l256feature defines the requirements for a register size of AVXKind.AVXSize.YMM. If any of those features is null, a VEX prefix is used for the corresponding register size.

The Opmask (opmask) register is only used when emitting an EVEX prefix.

z and b denote bits in the EVEX prefix that define the merging/zeroing behavior and are unused when emitting a VEX prefix.

vexPrefix

public final boolean vexPrefix(Register dst,
                               Register nds,
                               AMD64Address src,
                               AVXKind.AVXSize size,
                               int pp,
                               int mmmmm,
                               int w,
                               int wEvex,
                               boolean checkAVX,
                               CPUFeature l128feature,
                               CPUFeature l256feature)

Emits a VEX or EVEX prefix depending on the target register length and the given feature requirements for variable-length (AMD64.CPUFeature.AVX512VL) AVX-512 instructions, where the source src operand is a memory location. Here, the z and b bits are unset (0) when emitting an EVEX prefix and no opmask register is assumed.

See Also:

#vexPrefix(Register, Register, Register, Register, AVXSize, int, int, int, int, boolean, CPUFeature, CPUFeature, int, int)

vexPrefix

public final boolean vexPrefix(Register dst,
                               Register nds,
                               AMD64Address src,
                               Register opmask,
                               AVXKind.AVXSize size,
                               int pp,
                               int mmmmm,
                               int w,
                               int wEvex,
                               boolean checkAVX,
                               CPUFeature l128feature,
                               CPUFeature l256feature,
                               int z,
                               int b)

Emits a VEX or EVEX prefix depending on the target register length and the given feature requirements for variable-length (AMD64.CPUFeature.AVX512VL) AVX-512 instructions, where the source src operand is a memory location.

See Also:

#vexPrefix(Register, Register, Register, Register, AVXSize, int, int, int, int, boolean, CPUFeature, CPUFeature, int, int)

evexPrefix

protected final void evexPrefix(Register dst,
                                Register mask,
                                Register nds,
                                Register src,
                                AVXKind.AVXSize size,
                                int pp,
                                int mm,
                                int w,
                                int z,
                                int b)

Helper method for emitting EVEX prefix in the form of RRRR.

evexPrefix

protected final void evexPrefix(Register dst,
                                Register mask,
                                Register nds,
                                AMD64Address src,
                                AVXKind.AVXSize size,
                                int pp,
                                int mm,
                                int w,
                                int z,
                                int b)

Helper method for emitting EVEX prefix in the form of RRRM. Because the memory addressing in EVEX-encoded instructions employ a compressed displacement scheme when using disp8 form, the user of this API should make sure to encode the operands using AMD64BaseAssembler.emitOperandHelper(Register, AMD64Address, int, int).