| Interface | Description |
|---|---|
| AMD64ArithmeticLIRGeneratorTool |
This interface can be used to generate AMD64 LIR for arithmetic operations.
|
| Class | Description |
|---|---|
| AMD64AddressValue | |
| AMD64Arithmetic.FPDivRemOp | |
| AMD64ArrayCompareToOp |
Emits code which compares two arrays lexicographically.
|
| AMD64ArrayCopyWithConversionsOp |
Arraycopy operation for arbitrary source and destination arrays, with arbitrary byte offset, with
support for arbitrary compression and inflation of
8 bit,
16 bit or 32 bit array elements. |
| AMD64ArrayEqualsOp |
Emits code which compares two arrays of the same length.
|
| AMD64ArrayIndexOfOp | |
| AMD64ArrayRegionCompareToOp |
Emits code to compare two array regions lexicographically, using SIMD instructions where
possible.
|
| AMD64Binary |
AMD64 LIR instructions that have two inputs and one output.
|
| AMD64Binary.CommutativeTwoOp |
Commutative instruction that has two
AllocatableValue operands. |
| AMD64Binary.ConstOp |
Instruction that has one
AllocatableValue operand and one 32-bit immediate operand. |
| AMD64Binary.DataTwoOp |
Instruction that has one
AllocatableValue operand and one
DataSectionReference operand. |
| AMD64Binary.MemoryTwoOp |
Instruction that has one
AllocatableValue operand and one memory operand. |
| AMD64Binary.RMIOp |
Instruction with a separate result operand, one
AllocatableValue input and one 32-bit
immediate input. |
| AMD64Binary.TwoOp |
Instruction that has two
AllocatableValue operands. |
| AMD64BinaryConsumer |
AMD64 LIR instructions that have two input operands, but no output operand.
|
| AMD64BinaryConsumer.ConstOp |
Instruction that has one
AllocatableValue operand and one 32-bit immediate operand. |
| AMD64BinaryConsumer.DataOp |
Instruction that has one
AllocatableValue operand and one
DataSectionReference operand. |
| AMD64BinaryConsumer.MemoryConstOp |
Instruction that has one
memory operand and one 32-bit immediate
operand. |
| AMD64BinaryConsumer.MemoryMROp |
Instruction that has a
memory operand as first input and an
AllocatableValue as second input. |
| AMD64BinaryConsumer.MemoryRMOp |
Instruction that has an
AllocatableValue as first input and a
memory operand as second input. |
| AMD64BinaryConsumer.MemoryVMConstOp |
Instruction that has one
memory operand and one 32-bit immediate
operand that needs to be patched at runtime. |
| AMD64BinaryConsumer.Op |
Instruction that has two
AllocatableValue operands. |
| AMD64BinaryConsumer.VMConstOp |
Instruction that has one
AllocatableValue operand and one 32-bit immediate operand
that needs to be patched at runtime. |
| AMD64BlockEndOp | |
| AMD64BreakpointOp |
Emits a breakpoint.
|
| AMD64ByteSwapOp | |
| AMD64CacheWritebackOp |
Implements
jdk.internal.misc.Unsafe.writeback0(long). |
| AMD64CacheWritebackPostSyncOp |
Implements
jdk.internal.misc.Unsafe.writebackPostSync0(long). |
| AMD64CalcStringAttributesOp |
This intrinsic calculates the code range and codepoint length of strings in various encodings.
|
| AMD64Call | |
| AMD64Call.CallOp | |
| AMD64Call.DirectCallOp | |
| AMD64Call.DirectFarForeignCallOp | |
| AMD64Call.DirectNearForeignCallOp | |
| AMD64Call.ForeignCallOp | |
| AMD64Call.IndirectCallOp | |
| AMD64Call.MethodCallOp | |
| AMD64CCall | |
| AMD64ClearRegisterOp | |
| AMD64ComplexVectorOp |
Base class for AMD64 LIR instruction using AVX CPU features.
|
| AMD64ControlFlow | |
| AMD64ControlFlow.BranchOp | |
| AMD64ControlFlow.CmpBranchOp | |
| AMD64ControlFlow.CmpConstBranchOp | |
| AMD64ControlFlow.CmpDataBranchOp | |
| AMD64ControlFlow.CondMoveOp | |
| AMD64ControlFlow.CondSetOp | |
| AMD64ControlFlow.FloatBranchOp | |
| AMD64ControlFlow.FloatCondMoveOp | |
| AMD64ControlFlow.FloatCondSetOp | |
| AMD64ControlFlow.HashTableSwitchOp | |
| AMD64ControlFlow.RangeTableSwitchOp | |
| AMD64ControlFlow.StrategySwitchOp | |
| AMD64ControlFlow.TestBranchOp | |
| AMD64ControlFlow.TestByteBranchOp | |
| AMD64ControlFlow.TestConstBranchOp | |
| AMD64EncodeArrayOp | |
| AMD64FrameMap |
AMD64 specific frame map.
|
| AMD64FrameMapBuilder | |
| AMD64HasNegativesOp | |
| AMD64HotSpotHelper | |
| AMD64LFenceOp | |
| AMD64LIRInstruction |
Convenience class to provide AMD64MacroAssembler for the
AMD64LIRInstruction.emitCode(org.graalvm.compiler.lir.asm.CompilationResultBuilder) method. |
| AMD64MathCopySignOp | |
| AMD64MathCosOp |
ALGORITHM DESCRIPTION - COS()
---------------------
1.
|
| AMD64MathExpOp |
ALGORITHM DESCRIPTION - EXP()
---------------------
Description:
Let K = 64 (table size).
|
| AMD64MathIntrinsicBinaryOp |
AMD64MathIntrinsicBinaryOp assumes that the input values are stored in the xmm0 and xmm1
registers, and it will emit the output value into the xmm0 register.
|
| AMD64MathIntrinsicUnaryOp |
AMD64MathIntrinsicUnaryOp assumes that the input value is stored at the xmm0 register, and will
emit the output value into the xmm0 register as well.
|
| AMD64MathLog10Op |
ALGORITHM DESCRIPTION - LOG10()
---------------------
Let x=2^k * mx, mx in [1,2)
Get B~1/mx based on the output of rcpss instruction (B0)
B = int((B0*LH*2^7+0.5))/2^7
LH is a short approximation for log10(e)
Reduced argument: r=B*mx-LH (computed accurately in high and low parts)
Result: k*log10(2) - log(B) + p(r)
p(r) is a degree 7 polynomial
-log(B) read from data table (high, low parts)
Result is formed from high and low parts.
|
| AMD64MathLogOp |
ALGORITHM DESCRIPTION - LOG()
---------------------
x=2^k * mx, mx in [1,2)
Get B~1/mx based on the output of rcpss instruction (B0)
B = int((B0*2^7+0.5))/2^7
Reduced argument: r=B*mx-1.0 (computed accurately in high and low parts)
Result: k*log(2) - log(B) + p(r) if |x-1| >= small value (2^-6) and
p(r) is a degree 7 polynomial
-log(B) read from data table (high, low parts)
Result is formed from high and low parts.
|
| AMD64MathPowOp |
ALGORITHM DESCRIPTION - POW()
---------------------
Let x=2^k * mx, mx in [1,2)
log2(x) calculation:
Get B~1/mx based on the output of rcpps instruction (B0)
B = int((B0*LH*2^9+0.5))/2^9
LH is a short approximation for log2(e)
Reduced argument, scaled by LH:
r=B*mx-LH (computed accurately in high and low parts)
log2(x) result: k - log2(B) + p(r)
p(r) is a degree 8 polynomial
-log2(B) read from data table (high, low parts)
log2(x) is formed from high and low parts
For |x| in [1-1/32, 1+1/16), a slower but more accurate computation
based om the same table design is performed.
|
| AMD64MathSignumOp | |
| AMD64MathSinOp |
ALGORITHM DESCRIPTION - SIN()
---------------------
1.
|
| AMD64MathTanOp |
ALGORITHM DESCRIPTION - TAN()
---------------------
Polynomials coefficients and other constants.
|
| AMD64Move | |
| AMD64Move.AMD64MultiStackMove | |
| AMD64Move.AMD64PushPopStackMove | |
| AMD64Move.AMD64StackMove | |
| AMD64Move.AtomicReadAndAddOp | |
| AMD64Move.AtomicReadAndWriteOp | |
| AMD64Move.CompareAndSwapOp | |
| AMD64Move.CompressPointerOp | |
| AMD64Move.ConvertNullToZeroOp | |
| AMD64Move.ConvertZeroToNullOp | |
| AMD64Move.LeaDataOp | |
| AMD64Move.LeaOp | |
| AMD64Move.MembarOp | |
| AMD64Move.MoveFromConstOp | |
| AMD64Move.MoveFromRegOp | |
| AMD64Move.MoveToRegOp | |
| AMD64Move.NullCheckOp | |
| AMD64Move.PointerCompressionOp | |
| AMD64Move.StackLeaOp | |
| AMD64Move.UncompressPointerOp | |
| AMD64MulDivOp |
AMD64 mul/div operation.
|
| AMD64PauseOp |
Emits a pause.
|
| AMD64PrefetchOp | |
| AMD64ReadTimestampCounter |
AMD64 rdtsc operation.
|
| AMD64ReadTimestampCounterWithProcid |
AMD64 rdtscp operation.
|
| AMD64RestoreRegistersOp |
Restores registers from stack slots.
|
| AMD64RoundFloatToIntegerOp |
Round float to integer.
|
| AMD64SaveRegistersOp |
Saves registers to stack slots.
|
| AMD64ShiftOp |
AMD64 shift/rotate operation.
|
| AMD64SignExtendOp | |
| AMD64StrideUtil |
This class provides utility methods for "stride-agnostic" intrinsic ops such as
AMD64ArrayRegionCompareToOp. |
| AMD64StringLatin1InflateOp | |
| AMD64StringUTF16CompressOp | |
| AMD64Ternary |
AMD64 LIR instructions that have three inputs and one output.
|
| AMD64Ternary.ThreeOp |
Instruction that has two
AllocatableValue operands. |
| AMD64Unary |
AMD64 LIR instructions that have one input and one output.
|
| AMD64Unary.MemoryOp |
Instruction with a
memory operand. |
| AMD64Unary.MOp |
Instruction with a single operand that is both input and output.
|
| AMD64Unary.MROp |
Instruction with separate input and output operands, and an operand encoding of MR.
|
| AMD64Unary.RMOp |
Instruction with separate input and output operands, and an operand encoding of RM.
|
| AMD64UnaryConsumer |
AMD64 LIR instructions that have one input and no output.
|
| AMD64UnaryConsumer.MemoryOp | |
| AMD64VZeroUpper |
vzeroupper is essential to avoid performance penalty during SSE-AVX transition.
|
| AMD64ZapRegistersOp |
Writes well known garbage values to registers.
|
| AMD64ZapStackOp |
Writes well known garbage values to stack slots.
|
| AMD64ZeroMemoryOp |
Zeros a chunk of memory using rep stosb.
|
| Enum | Description |
|---|---|
| AMD64Arithmetic | |
| AMD64CalcStringAttributesOp.Op |