public static class AMD64VectorBlend.EvexBlendOp extends AMD64LIRInstruction implements AVX512Support
LIRInstruction.Alive, LIRInstruction.Def, LIRInstruction.OperandFlag, LIRInstruction.OperandMode, LIRInstruction.State, LIRInstruction.Temp, LIRInstruction.Use| Modifier and Type | Field and Description |
|---|---|
static LIRInstructionClass<AMD64VectorBlend.EvexBlendOp> |
TYPE |
ADDRESS_FLAGS, ALLOWED_FLAGS| Constructor and Description |
|---|
EvexBlendOp(AMD64Assembler.VexRVMOp opcode,
AVXKind.AVXSize size,
AllocatableValue result,
AllocatableValue x,
AllocatableValue y,
AllocatableValue mask) |
| Modifier and Type | Method and Description |
|---|---|
void |
emitCode(CompilationResultBuilder crb,
AMD64MacroAssembler masm) |
AllocatableValue |
getOpmask()
Denotes the optional opmask register that allows additional masking for write operations.
|
emitCodeaddStackSlotsToTemporaries, destroysCallerSavedRegisters, forEachAlive, forEachAlive, forEachInput, forEachInput, forEachOutput, forEachOutput, forEachRegisterHint, forEachRegisterHint, forEachState, forEachState, forEachState, forEachState, forEachTemp, forEachTemp, getComment, getLIRInstructionClass, getPosition, hashCode, hasOperands, hasState, id, isLoadConstantOp, isMoveOp, isValueMoveOp, name, needsClearUpperVectorRegisters, setComment, setId, setPosition, toString, toString, toStringWithIdPrefix, verify, visitEachAlive, visitEachAlive, visitEachInput, visitEachInput, visitEachOutput, visitEachOutput, visitEachState, visitEachState, visitEachTemp, visitEachTempclone, equals, getClass, notify, notifyAll, wait, wait, waitgetOpmaskRegisterpublic static final LIRInstructionClass<AMD64VectorBlend.EvexBlendOp> TYPE
public EvexBlendOp(AMD64Assembler.VexRVMOp opcode, AVXKind.AVXSize size, AllocatableValue result, AllocatableValue x, AllocatableValue y, AllocatableValue mask)
public void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm)
emitCode in class AMD64LIRInstructionpublic AllocatableValue getOpmask()
AVX512SupportValue.getValueKind() should correspond to the operand registers in such a way that all
lanes may be masked (e.g. 8 bits for 512 bit QWORDs in a ZMM register). May be
Value.ILLEGAL if no register should be used.getOpmask in interface AVX512SupportValue.ILLEGAL