org.graalvm.compiler.lir.amd64.vector

Class AMD64VectorShuffle.ShuffleWordOpWithMask

java.lang.Object

org.graalvm.compiler.lir.LIRInstruction

org.graalvm.compiler.lir.amd64.AMD64LIRInstruction

org.graalvm.compiler.lir.amd64.vector.AMD64VectorShuffle.ShuffleWordOp

org.graalvm.compiler.lir.amd64.vector.AMD64VectorShuffle.ShuffleWordOpWithMask

All Implemented Interfaces:

AVX512Support

Enclosing class:

AMD64VectorShuffle

public static class AMD64VectorShuffle.ShuffleWordOpWithMask
extends AMD64VectorShuffle.ShuffleWordOp
implements AVX512Support

Nested Class Summary

Nested classes/interfaces inherited from class org.graalvm.compiler.lir.LIRInstruction

LIRInstruction.Alive, LIRInstruction.Def, LIRInstruction.OperandFlag, LIRInstruction.OperandMode, LIRInstruction.State, LIRInstruction.Temp, LIRInstruction.Use

Field Summary

Fields

Modifier and Type	Field and Description
protected AllocatableValue	mask
static LIRInstructionClass<AMD64VectorShuffle.ShuffleWordOpWithMask>	TYPE

Fields inherited from class org.graalvm.compiler.lir.amd64.vector.AMD64VectorShuffle.ShuffleWordOp

op, result, selector, source

Fields inherited from class org.graalvm.compiler.lir.LIRInstruction

ADDRESS_FLAGS, ALLOWED_FLAGS

Constructor Summary

Constructors

Constructor and Description
ShuffleWordOpWithMask(AMD64Assembler.VexRMIOp op, AllocatableValue result, AllocatableValue source, int selector, AllocatableValue mask)

Method Summary

Modifier and Type	Method and Description
void	emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm)
AllocatableValue	getOpmask() Denotes the optional opmask register that allows additional masking for write operations.

Methods inherited from class org.graalvm.compiler.lir.amd64.AMD64LIRInstruction

emitCode

Methods inherited from class org.graalvm.compiler.lir.LIRInstruction

addStackSlotsToTemporaries, destroysCallerSavedRegisters, forEachAlive, forEachAlive, forEachInput, forEachInput, forEachOutput, forEachOutput, forEachRegisterHint, forEachRegisterHint, forEachState, forEachState, forEachState, forEachState, forEachTemp, forEachTemp, getComment, getLIRInstructionClass, getPosition, hashCode, hasOperands, hasState, id, isLoadConstantOp, isMoveOp, isValueMoveOp, name, needsClearUpperVectorRegisters, setComment, setId, setPosition, toString, toString, toStringWithIdPrefix, verify, visitEachAlive, visitEachAlive, visitEachInput, visitEachInput, visitEachOutput, visitEachOutput, visitEachState, visitEachState, visitEachTemp, visitEachTemp

Methods inherited from class java.lang.Object

clone, equals, getClass, notify, notifyAll, wait, wait, wait

Methods inherited from interface org.graalvm.compiler.lir.amd64.vector.AVX512Support

getOpmaskRegister

Field Detail

TYPE

public static final LIRInstructionClass<AMD64VectorShuffle.ShuffleWordOpWithMask> TYPE

mask

protected AllocatableValue mask

Constructor Detail

ShuffleWordOpWithMask

public ShuffleWordOpWithMask(AMD64Assembler.VexRMIOp op,
                             AllocatableValue result,
                             AllocatableValue source,
                             int selector,
                             AllocatableValue mask)

Method Detail

emitCode

public void emitCode(CompilationResultBuilder crb,
                     AMD64MacroAssembler masm)

Overrides:

emitCode in class AMD64VectorShuffle.ShuffleWordOp

getOpmask

public AllocatableValue getOpmask()

Description copied from interface: AVX512Support

Denotes the optional opmask register that allows additional masking for write operations. The Value.getValueKind() should correspond to the operand registers in such a way that all lanes may be masked (e.g. 8 bits for 512 bit QWORDs in a ZMM register). May be Value.ILLEGAL if no register should be used.

Specified by:

getOpmask in interface AVX512Support

Returns:

a register that contains the opmask operand or Value.ILLEGAL