public static final class AMD64VectorUnary.AVXBroadcastOp extends AMD64VectorInstruction implements AVX512Support
LIRInstruction.Alive, LIRInstruction.Def, LIRInstruction.OperandFlag, LIRInstruction.OperandMode, LIRInstruction.State, LIRInstruction.Temp, LIRInstruction.Use| Modifier and Type | Field and Description |
|---|---|
protected Value |
input |
protected AllocatableValue |
opmask |
protected AllocatableValue |
result |
static LIRInstructionClass<AMD64VectorUnary.AVXBroadcastOp> |
TYPE |
sizeADDRESS_FLAGS, ALLOWED_FLAGS| Constructor and Description |
|---|
AVXBroadcastOp(AMD64Assembler.VexRMOp opcode,
AVXKind.AVXSize size,
AllocatableValue result,
Value input) |
AVXBroadcastOp(AMD64Assembler.VexRMOp opcode,
AVXKind.AVXSize size,
AllocatableValue result,
Value input,
AllocatableValue opmask,
int z,
int b) |
| Modifier and Type | Method and Description |
|---|---|
void |
emitCode(CompilationResultBuilder crb,
AMD64MacroAssembler masm) |
AllocatableValue |
getOpmask()
Denotes the optional opmask register that allows additional masking for write operations.
|
needsClearUpperVectorRegistersemitCodeaddStackSlotsToTemporaries, destroysCallerSavedRegisters, forEachAlive, forEachAlive, forEachInput, forEachInput, forEachOutput, forEachOutput, forEachRegisterHint, forEachRegisterHint, forEachState, forEachState, forEachState, forEachState, forEachTemp, forEachTemp, getComment, getLIRInstructionClass, getPosition, hashCode, hasOperands, hasState, id, isLoadConstantOp, isMoveOp, isValueMoveOp, name, setComment, setId, setPosition, toString, toString, toStringWithIdPrefix, verify, visitEachAlive, visitEachAlive, visitEachInput, visitEachInput, visitEachOutput, visitEachOutput, visitEachState, visitEachState, visitEachTemp, visitEachTempclone, equals, getClass, notify, notifyAll, wait, wait, waitgetOpmaskRegisterpublic static final LIRInstructionClass<AMD64VectorUnary.AVXBroadcastOp> TYPE
protected AllocatableValue result
protected Value input
protected AllocatableValue opmask
public AVXBroadcastOp(AMD64Assembler.VexRMOp opcode, AVXKind.AVXSize size, AllocatableValue result, Value input)
public AVXBroadcastOp(AMD64Assembler.VexRMOp opcode, AVXKind.AVXSize size, AllocatableValue result, Value input, AllocatableValue opmask, int z, int b)
public AllocatableValue getOpmask()
AVX512SupportValue.getValueKind() should correspond to the operand registers in such a way that all
lanes may be masked (e.g. 8 bits for 512 bit QWORDs in a ZMM register). May be
Value.ILLEGAL if no register should be used.getOpmask in interface AVX512SupportValue.ILLEGALpublic void emitCode(CompilationResultBuilder crb, AMD64MacroAssembler masm)
emitCode in class AMD64LIRInstruction